scholarly journals Blue Electroluminescent Al2O3/Tm2O3 Nanolaminate Films Fabricated by Atomic Layer Deposition on Silicon

Nanomaterials ◽  
2019 ◽  
Vol 9 (3) ◽  
pp. 413 ◽  
Author(s):  
Yao Liu ◽  
Zhongtao Ouyang ◽  
Li Yang ◽  
Yang Yang ◽  
Jiaming Sun
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Impact Excitation ◽  
Precise Control ◽  
Decay Lifetime ◽  
Layer Deposition ◽  
Sublayer Thickness ◽  
Silicon Based ◽  
The Impact

Realization of a silicon-based light source is of significant importance for the future development of optoelectronics and telecommunications. Here, nanolaminate Al2O3/Tm2O3 films are fabricated on silicon utilizing atomic layer deposition, and intense blue electroluminescence (EL) from Tm3+ ions is achieved in the metal-oxide-semiconductor structured luminescent devices based on them. Precise control of the nanolaminates enables the study on the influence of the Tm dopant layers and the distance between every Tm2O3 layer on the EL performance. The 456 nm blue EL from Tm3+ ions shows a maximum power density of 0.15 mW/cm2. The EL intensities and decay lifetime decrease with excessive Tm dopant cycles due to the reduction of optically active Tm3+ ions. Cross-relaxation among adjacent Tm2O3 dopant layers reduces the blue EL intensity and the decay lifetime, which strongly depends on the Al2O3 sublayer thickness, with a critical value of ~3 nm. The EL is attributed to the impact excitation of the Tm3+ ions by hot electrons in Al2O3 matrix via Poole–Frenkel mechanism.

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Trap states in AlGaN/GaN metal-oxide-semiconductor structures with Al2O3 prepared by atomic layer deposition

2010 ◽  
Vol 107 (10) ◽  
pp. 106104 ◽  
Author(s):  
D. Gregušová ◽  
R. Stoklas ◽  
Ch. Mizue ◽  
Y. Hori ◽  
J. Novák ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Metal Oxide ◽  
Atomic Layer ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Trap States ◽  
Semiconductor Structures ◽  
Layer Deposition

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

Development of High-Quality Gate Oxide on 4H-SiC Using Atomic Layer Deposition

2020 ◽  
Vol 1004 ◽  
pp. 547-553
Author(s):  
A.B. Renz ◽  
Oliver J. Vavasour ◽  
Peter M. Gammon ◽  
Fan Li ◽  
Tian Dai ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Photoelectron Spectroscopy ◽  
Elevated Temperatures ◽  
Dielectric Breakdown ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Gas Treatment ◽  
Time Dependent Dielectric Breakdown ◽  
Layer Deposition ◽  
Order Of Magnitude

A systematic post-deposition annealing study on Silicon Carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) using atomic layer deposition (ALD)-deposited silicon dioxide (SiO2) layers was carried out. Anneals were done in oxidising (N2O), inert (Ar) and reducing (H2:N2) ambients at elevated temperatures from 900°C to 1300°C for 1 hour. Electrical characterisation results show that the forming gas treatment at 1100°C reduces the flatband voltage to 0.23 V from 10 V for as-deposited SiO2 layers. The density of interface traps (DIT) was also reduced by one order of magnitude to 2×1011 cm-2 eV-1 at EC-ET = 0.2 eV. As an indicator of the improvement, characterisation by x-ray photoelectron spectroscopy (XPS) showed that silicon enrichment present in as-deposited layers was largely reduced by the forming gas anneal, improving the stoichiometry. Time-dependent dielectric breakdown (TDDB) results showed that the majority of forming gas annealed samples broke down at breakdown fields of 12.5 MV × cm-1, which is about 2.5 MV × cm-1 higher than for thermally oxidised samples.

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