scholarly journals Assessment of the Accuracy of Determining the Angular Position of the Unmanned Bathymetric Surveying Vehicle Based on the Sea Horizon Image

Sensors ◽  
2019 ◽  
Vol 19 (21) ◽  
pp. 4644 ◽  
Author(s):  
Naus ◽  
Marchel ◽  
Szymak ◽  
Nowak
Keyword(s):  
Angular Position ◽  
Complementary Metal Oxide Semiconductor ◽  
General Concept ◽  
Oxide Semiconductor ◽  
Position Measurement ◽  
The Matrix ◽  
Horizon Line ◽  
Aerial Vehicle ◽  
Line Slope ◽  
Further Development

The paper presents the results of research on assessing the accuracy of angular position measurement relative to the sea horizon using a camera mounted on an unmanned bathymetric surveying vehicle of the Unmanned Surface Vehicle (USV) or Unmanned Aerial Vehicle (UAV) type. The first part of the article presents the essence of the problem. The rules of taking the angular position of the vehicle into account in bathymetric surveys and the general concept of the two-camera tilt compensator were described. The second part presents a mathematical description of the meters characterizing a resolution and a mean error of measurements, made on the base of the horizon line image, recorded with an optical system with a Complementary Metal-Oxide Semiconductor (CMOS) matrix. The phenomenon of the horizon line curvature in the image projected onto the matrix that appears with the increase of the camera height has been characterized. The third part contains an example of a detailed analysis of selected cameras mounted on UAVs manufactured by DJI, carried out using the proposed meters. The obtained results including measurement resolutions of a single-pixel and mean errors of the horizon line slope measurement were presented in the form of many tables and charts with extensive comments. The final part presents the general conclusions from the performed research and a proposal of directions for their further development.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

scholarly journals Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1272
Author(s):  
Zhihua Fan ◽  
Qinling Deng ◽  
Xiaoyu Ma ◽  
Shaolin Zhou
Keyword(s):  
Phase Change ◽  
Phase Change Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nanophotonic Devices ◽  
Optoelectronic Integration ◽  
Hybrid Devices ◽  
Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

scholarly journals CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

2018 ◽  
Vol 7 (2.7) ◽  
pp. 647
Author(s):  
J Lakshmi Prasanna ◽  
V Sahiti ◽  
E Raghuveera ◽  
M Ravi Kumar
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Tree Structure ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Prefix Tree ◽  
Digital Comparator ◽  
Parallel Prefix ◽  
Transmission Gates

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs. 

scholarly journals Atomic-scale structure and chemical sensing application of ultrasmall size-selected Pt nanoparticles supported on SnO2

2020 ◽  
Vol 1 (9) ◽  
pp. 3200-3207
Author(s):  
Stephan Steinhauer ◽  
Eva Lackner ◽  
Florentyna Sosada-Ludwikowska ◽  
Vidyadhar Singh ◽  
Johanna Krainer ◽  
...  
Keyword(s):  
Carbon Monoxide ◽  
Chemical Sensing ◽  
Pt Nanoparticles ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Atomic Scale ◽  
Oxide Semiconductor ◽  
Semiconductor Technology ◽  
Sensing Application ◽  
Chemoresistive Sensors

SnO2-based chemoresistive sensors integrated in complementary metal-oxide-semiconductor technology were functionalized with ultrasmall Pt nanoparticles, resulting in carbon monoxide sensing properties with minimized humidity interference.

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