scholarly journals Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs

2021 ◽  
Author(s):  
Takamasa KAWANAGO ◽  
Takahiro Matsuzaki ◽  
Ryosuke Kajikawa ◽  
Iriya Muneta ◽  
Takuya HOSHII ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Supply Voltage ◽  
Transition Metal Dichalcogenides ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Poly Vinyl Alcohol ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Power Supply Voltage ◽  
Doping Technique

Abstract In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (Vdd), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at Vdd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides (TMDC)-based devices and circuits.

scholarly journals Melt Blown Fiber-Assisted Solvent-Free Device Fabrication at Low-Temperature

Micromachines ◽  
2020 ◽  
Vol 11 (12) ◽  
pp. 1091
Author(s):  
Minjong Lee ◽  
Joohoon Kang ◽  
Young Tack Lee
Keyword(s):  
Transition Metal Dichalcogenides ◽  
Hole Mobility ◽  
Device Fabrication ◽  
Solvent Free ◽  
Oxide Semiconductor ◽  
Drain Voltage ◽  
Cmos Inverter ◽  
Current Ratio ◽  
Metal Dichalcogenides ◽  
P Type

In this paper, we propose a solvent-free device fabrication method using a melt-blown (MB) fiber to minimize potential chemical and thermal damages to transition-metal-dichalcogenides (TMDCs)-based semiconductor channel. The fabrication process is composed of three steps; (1) MB fibers alignment as a shadow mask, (2) metal deposition, and (3) lifting-up MB fibers. The resulting WSe2-based p-type metal-oxide-semiconductor (PMOS) device shows an ON/OFF current ratio of ~2 × 105 (ON current of ~−40 µA) and a remarkable linear hole mobility of ~205 cm2/V·s at a drain voltage of −0.1 V. These results can be a strong evidence supporting that this MB fiber-assisted device fabrication can effectively suppress materials damage by minimizing chemical and thermal exposures. Followed by an MoS2-based n-type MOS (NMOS) device demonstration, a complementary MOS (CMOS) inverter circuit application was successfully implemented, consisted of an MoS2 NMOS and a WSe2 PMOS as a load and a driver transistor, respectively. This MB fiber-based device fabrication can be a promising method for future electronics based on chemically reactive or thermally vulnerable materials.

MOSFET Gate Oxide Reliability: Anode Hole Injection Model and its Applications

2001 ◽  
Vol 11 (03) ◽  
pp. 849-886 ◽  
Author(s):  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
Theoretical Foundation ◽  
Supply Voltage ◽  
Operating Time ◽  
Hole Injection ◽  
Power Supply Voltage ◽  
Oxide Reliability ◽  
Injection Model ◽  
Anode Hole ◽  
Anode Hole Injection

We review the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric. The experimental and theoretical foundation of the AHI model is presented. Recent development and implications for the reliability of ultra-thin oxides are discussed. AHI is used to illuminate the questions of E versus 1/E models and field-driven versus voltage-driven models. Building on the concept of effective thinning, the AHI model is applied for the interpretation of defect-induced breakdown data and for optimizing oxide screening conditions. Circuit level reliability projection as a function of operating time, temperature, and power supply voltage is also illustrated.

Organic CMOS Technology Based on Interface Doped Pentacene

2005 ◽  
Vol 871 ◽  
Author(s):  
Marcus Ahles ◽  
Roland Schmechel ◽  
Heinz von Seggern
Keyword(s):  
Gate Voltage ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
Organic Systems ◽  
Electron Accumulation ◽  
P Type

AbstractAn organic complementary-metal-oxide-semiconductor (CMOS) inverter based on pentacene acting as both n- and p-type organic semiconductor is presented. The circuit consists of two spatially separated transistors which are realized within one continuous pentacene layer. Both transistors act exclusively in unipolar mode with electron and hole mobilities of 0.11 cm2V-1s-1 and 0.10 cm2V-1s-1, respectively. In the domain of the n-channel, electron accumulation in the pentacene is enabled by deposition of traces of calcium acting as electron donator. The CMOS inverter works reliably within the range of the supply voltage (60 V) with a gain in between 17 and 24 which is among the highest values observed in organic systems. Nevertheless, the circuit shows hysteresis, which is explained by a gate voltage depending trap occupation in the n-channel.

scholarly journals Categorization and Characterization of Time Domain CMOS Temperature Sensors

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6700
Author(s):  
Sangjin Byun
Keyword(s):  
Time Domain ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Temperature Sensors ◽  
Oxide Semiconductor ◽  
Voltage Sensitivity ◽  
Power Supply Voltage ◽  
Measured Time ◽  
Long Time ◽  
The Time Domain

Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.

scholarly journals Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

2020 ◽  
Vol 9 (12) ◽  
pp. 150-153
Keyword(s):  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Power Supply Voltage ◽  
Short Channel ◽  
Work Area ◽  
Strong Inversion ◽  
Surrounding Gate ◽  
Common Gate

In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout

2011 ◽  
Vol E94-C (6) ◽  
pp. 1072-1075
Author(s):  
Tadashi YASUFUKU ◽  
Yasumi NAKAMURA ◽  
Zhe PIAO ◽  
Makoto TAKAMIYA ◽  
Takayasu SAKURAI
Keyword(s):  
Power Supply ◽  
Voltage Dependence ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Place And Route ◽  
Delay Variation
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