scholarly journals Research on Two Stage and Folded Cascode Bulk Driven OTA in 0.18um CMOS Process

2019 ◽  
Vol 8 (6S4) ◽  
pp. 994-997
Keyword(s):  
Comparative Analysis ◽  
Power Consumption ◽  
Biomedical Applications ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Threshold Region ◽  
Test Results ◽  
High Input ◽  
Two Stage ◽  
Folded Cascode

This paper presence a comparative analysis of two stage and folded cascode bulk driven operational trans conductance amplifier (OTA) topologies for biomedical applications are presented. A two stage bulk driven OTA and Folded cascoded OTA operated with a 1Vpower supply. Bulkdriven PMOS-transistors as an input differential opamp provides high input common-mode range (CMR). To achieve low power consumption all transistors must be operated in sub threshold region. The test results are carried out in standard gpdk180nm CMOS technologies.

scholarly journals Research on Two stage and Folded Cascode Bulk Driven OTA in 0.18um CMOS Process

2019 ◽  
Vol 8 (9S2) ◽  
pp. 847-850
Keyword(s):  
Comparative Analysis ◽  
Power Consumption ◽  
Biomedical Applications ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Threshold Region ◽  
Test Results ◽  
High Input ◽  
Two Stage ◽  
Folded Cascode

This paper presence a comparative analysis of two stage and folded cascode bulk driven operational trans conductance amplifier (OTA) topologies for biomedical applications are presented. A two stage bulk driven OTA and Folded cascoded OTA operated with a 1Vpower supply. Bulkdriven PMOS-transistors as an input differential opamp provides high input common-mode range (CMR). To achieve low power consumption all transistors must be operated in sub threshold region. The test results are carried out in standard gpdk180nm CMOS technologies

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

A High-Performance Interface ASIC for Quartz Rate Sensor

2011 ◽  
Vol 483 ◽  
pp. 471-474
Author(s):  
Wei Ping Chen ◽  
Qing Yi Wang ◽  
Liang Yin ◽  
Zhi Ping Zhou
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Performance ◽  
Low Noise ◽  
Stable Operation ◽  
Cmos Process ◽  
Test Results ◽  
Bias Stability ◽  
Output Noise ◽  
Rate Sensor

In this work, an ASIC interface for quartz rate sensor (QRS) is introduced. Based on 0.6μm 18V N-well CMOS process, it is the first to be realized in the domestic. This chip has a minimized size of 5×4.4mm2. Compared with traditional interface constructed by separate devices, such interface implemented with integrated circuits is advantageous in size and power consumption. This satisfies the requirements of miniature and low power consumption in space industry and military domain. The test results show that this interface features low noise, high linearity, and stable operation. Integrated with the sensor, the entire system presents high performance in short term bias stability, nonlinearity, output noise, bias variation over temperature, and power consumption.

Research and Design of the DSRC Device Measuring Instrument

2014 ◽  
Vol 556-562 ◽  
pp. 2577-2580
Author(s):  
Xin You Li ◽  
Ze Bin Xu ◽  
Jin Xu Guo
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Radio Frequency ◽  
Low Power Consumption ◽  
Measuring Instrument ◽  
Test Results ◽  
The Core ◽  
Actual Operation ◽  
Design Proposal ◽  
Research And Design

Along with an increasingly wide utilization in the fields of ETC application, it becomes more and more important to measuring quickly and accurately on the key equipment of ETC system, such as OBU and RSU. This article is based on the measuring requirement of ETC system and propose a new design proposal by selecting STR715FR0 chip base on the core of ARM7TDMI series and 5.8GHz radio frequency transceiver circuit, the actual operation and test results show that the DSRC device Measuring Instrument works with stability, reliability and low power consumption, which enables convenient and efficient measuring to ensure the reliability and consistency of the ETC key equipment.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

Sign in / Sign up

Export Citation Format

Share Document