scholarly journals Optimization Method for Delay and Power Using Enhanced CSS FLIP FLOP with 24 Transistors

2020 ◽  
Vol 8 (6S) ◽  
pp. 116-119
Keyword(s):  
Power Dissipation ◽  
Optimization Method ◽  
New Method ◽  
Clock Signal ◽  
Flip Flop ◽  
Require Information

New way optimization method is an Enhanced CSS F 2A new method titled in this paper to explain the improved flip flop design with 24 transistor’s using circuit-shared static flipflop (ECSSFlip Flop).this implementation enhances power and delay where we utilize 5 NOR gates and 2 INV's(inverters), these methods are these methods are utilized in the quality cell libraries, The ECSS FLIP FLOP utilizes a positive intercessor clock signal, it is produced from a main clock, to require information into a main latch and a negative fringe of the foundation clock to carry the info during a gated latch. Cadence(Virtuoso) simulations at 180-μm found optimized at different frequency now the ability by a power dissipation of 9.516nW and delay by 3.634 ns in comparison to CSS FLIP FLOP

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Soccer Game Optimization

2015 ◽  
pp. 1434-1469 ◽  
Author(s):  
Hindriyanto Dwi Purnomo ◽  
Hui-Ming Wee
Keyword(s):  
Evolutionary Algorithm ◽  
Information Sharing ◽  
Swarm Intelligence ◽  
Soccer Player ◽  
Optimization Problems ◽  
Optimization Method ◽  
New Method ◽  
Intelligence Algorithm ◽  
Reproduction Process ◽  
Swarm Intelligence Algorithm

A new metaheuristic algorithm is proposed. The algorithm integrates the information sharing as well as the evolution operators in the swarm intelligence algorithm and evolutionary algorithm respectively. The basic soccer player movement is used as the analogy to describe the algorithm. The new method has two basic operators; the move off and the move forward. The proposed method elaborates the reproduction process in evolutionary algorithm with the powerful information sharing in the swarm intelligence algorithm. Examples of implementations are provided for continuous and discrete problems. The experiment results reveal that the proposed method has the potential to become a powerful optimization method. As a new method, the proposed algorithm can be enhanced in many different ways such as investigating the parameter setting, elaborating more aspects of the soccer player movement as well as implementing the proposed method to solve various optimization problems.

Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique

2017 ◽  
Vol 27 (02) ◽  
pp. 1850029 ◽  
Author(s):  
Bishnu Prasad De ◽  
Kanchan Baran Maji ◽  
Rajib Kar ◽  
Durbadal Mandal ◽  
Sakti Prasad Ghoshal
Keyword(s):  
Power Dissipation ◽  
Optimization Problems ◽  
Optimization Technique ◽  
Optimization Method ◽  
Vlsi Circuits ◽  
Optimal Designs ◽  
Efficient Design ◽  
Mos Transistors ◽  
Evolutionary Technique ◽  
Random Particle

This paper proposes an efficient design technique for two commonly used VLSI circuits, namely, CMOS current mirror load-based differential amplifier circuit and CMOS two-stage operational amplifier. The hybrid evolutionary method utilized for these optimal designs is random particle swarm optimization with differential evolution (RPSODE). Random PSO utilizes the weighted particles for monitoring the search directions. DE is a robust evolutionary technique. It has demonstrated an exclusive performance for the optimization problems which are continuous and global but suffers from the uncertainty issues. PSO is a robust optimization method but suffers from sub-optimality problem. This paper effectively hybridizes the random PSO and DE to remove the limitations related to both the techniques individually. In this paper, RPSODE is employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained from RPSODE technique are validated in SPICE environment. SPICE-based simulation results justify that RPSODE is a much better technique than other formerly reported methods for the designs of the above mentioned circuits in terms of MOS area, gain, power dissipation, etc.

scholarly journals Correntropy induced loss based sparse robust graph regularized extreme learning machine for cancer classification

2020 ◽  
Vol 21 (1) ◽  
Author(s):  
Liang-Rui Ren ◽  
Ying-Lian Gao ◽  
Jin-Xing Liu ◽  
Junliang Shang ◽  
Chun-Hou Zheng
Keyword(s):  
Extreme Learning Machine ◽  
High Performance ◽  
Structural Information ◽  
Optimization Method ◽  
Classification Performance ◽  
Weight Matrix ◽  
New Method ◽  
Classification Problems ◽  
Graph Regularization ◽  
Learning Machine

Abstract Background As a machine learning method with high performance and excellent generalization ability, extreme learning machine (ELM) is gaining popularity in various studies. Various ELM-based methods for different fields have been proposed. However, the robustness to noise and outliers is always the main problem affecting the performance of ELM. Results In this paper, an integrated method named correntropy induced loss based sparse robust graph regularized extreme learning machine (CSRGELM) is proposed. The introduction of correntropy induced loss improves the robustness of ELM and weakens the negative effects of noise and outliers. By using the L2,1-norm to constrain the output weight matrix, we tend to obtain a sparse output weight matrix to construct a simpler single hidden layer feedforward neural network model. By introducing the graph regularization to preserve the local structural information of the data, the classification performance of the new method is further improved. Besides, we design an iterative optimization method based on the idea of half quadratic optimization to solve the non-convex problem of CSRGELM. Conclusions The classification results on the benchmark dataset show that CSRGELM can obtain better classification results compared with other methods. More importantly, we also apply the new method to the classification problems of cancer samples and get a good classification effect.

An Improved Method for Gas Lift Allocation Optimization

1995 ◽  
Vol 117 (2) ◽  
pp. 87-92 ◽  
Author(s):  
N. Nishikiori ◽  
R. A. Redner ◽  
D. R. Doty ◽  
Z. Schmidt
Keyword(s):  
Optimization Technique ◽  
Gas Injection ◽  
Initial Point ◽  
Optimization Method ◽  
New Method ◽  
Superior Performance ◽  
Total Oil ◽  
Quasi Newton ◽  
Gas Lift ◽  
Injection Rates

A new method for finding the optimum gas injection rates for a group of continuous gas lift wells to maximize the total oil production rate is established. The new method uses a quasi-Newton nonlinear optimization technique which is incorporated with the gradient projection method. The method is capable of accommodating restrictions to the gas injection rates. The only requirement for fast convergence is that a reasonable estimate of the gas injection rates must be supplied as an initial point to the optimization method. A method of estimating the gas injection rates is developed for that purpose. A computer program is developed capable of implementing the new optimization method as well as generating the initial estimate of the gas injection rates. This program is then successfully tested on field data under both unlimited and limited gas supply. The new optimization technique demonstrates superior performance, faster convergence, and greater application.

Design of a novel quantum reversible ternary up-counter

2015 ◽  
Vol 13 (05) ◽  
pp. 1550038 ◽  
Author(s):  
Pouran Houshmand ◽  
Majid Haghparast
Keyword(s):  
Power Dissipation ◽  
Reversible Logic ◽  
Sequential Circuits ◽  
Utilization Rate ◽  
Time And Space ◽  
Space Utilization ◽  
Flip Flop ◽  
New Approach ◽  
Combinational And Sequential Circuits ◽  
Better Than

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.

Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

2014 ◽  
Vol 573 ◽  
pp. 187-193 ◽  
Author(s):  
Anitha Ponnusamy ◽  
Palaniappan Ramanathan
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
High Speed ◽  
Total Power ◽  
Single Chip ◽  
Flip Flop ◽  
Design And Optimization ◽  
Negative Edge ◽  
Carry Select Adder ◽  
Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

Sign in / Sign up

Export Citation Format

Share Document