Cell Processing for Two Scientific Computing Kernels

2010 ◽  
pp. 312-336
Author(s):  
Meilian Xu ◽  
Parimala Thulasiraman ◽  
Ruppa K. Thulasiram
Keyword(s):  
High Speed ◽  
Scientific Computing ◽  
Building Blocks ◽  
Data Locality ◽  
Data Mapping ◽  
Single Chip ◽  
Data Intensive ◽  
Synchronization Overhead ◽  
Simd Processing ◽  
On Chip

This chapter uses two scientific computing kernels to illustrate challenges of designing parallel algorithms for one heterogeneous multi-core processor, the Cell Broadband Engine processor (Cell/B.E.). It describes the limitation of the current parallel systems using single-core processors as building blocks. The limitation deteriorates the performance of applications which have data-intensive and computationintensive kernels such as Finite Difference Time Domain (FDTD) and Fast Fourier Transform (FFT). FDTD is a regular problem with nearest neighbour comminuncation pattern under synchronization constraint. FFT based on indirect swap network (ISN) modifies the data mapping in traditional Cooley- Tukey butterfly network to improve data locality, hence reducing the communication and synchronization overhead. The authors hope to unleash the Cell/B.E. and design parallel FDTD and parallel FFT based on ISN by taking into account unique features of Cell/B.E. such as its eight SIMD processing units on the single chip and its high-speed on-chip bus.

122 GHz single-chip dual-channel SMD radar sensor with on-chip antennas for distance and angle measurements

2015 ◽  
Vol 7 (3-4) ◽  
pp. 407-414 ◽  
Author(s):  
Mekdes G. Girma ◽  
Markus Gonser ◽  
Andreas Frischen ◽  
Jürgen Hasch ◽  
Yaoming Sun ◽  
...  
Keyword(s):  
Building Blocks ◽  
Single Chip ◽  
Fully Integrated ◽  
Dual Channel ◽  
Angle Measurements ◽  
Bicmos Technology ◽  
Measurement Results ◽  
Sige Bicmos ◽  
On Chip ◽  
Digital Processor

This paper describes the design considerations, integration issues, packaging, and experimental performance of recently developed D-Band dual-channel transceiver with on-chip antennas fabricated in a SiGe-BiCMOS technology. The design comprises a fully integrated transceiver circuit with quasi-monostatic architecture that operates between 114 and 124 GHz. All analog building blocks are controllable via a serial peripheral interface to reduce the number of connections and facilitate the communication between digital processor and analog building blocks. The two electromagnetically coupled patch antennas are placed on the top of the die with 8.6 dBi gain and have a simulated efficiency of 60%. The chip consumes 450 mW and is wire-bonded into an open-lid 5 × 5 mm2quad-flat no-leads package. Measurement results for the estimation of range, and azimuth angle in single object situation are presented.

Nanoelectronics

2021 ◽  
pp. 20-35
Author(s):  
Jutika Devi ◽  
Pranayee Datta
Keyword(s):  
Integrated Circuits ◽  
Communication Networks ◽  
Communication Systems ◽  
High Speed ◽  
Building Blocks ◽  
Power Efficient ◽  
Fifth Generation ◽  
Communication Links ◽  
On Chip ◽  
Passive Circuit

The passive circuit elements resistor, inductor, and capacitor, which are the basic building blocks of an electronic circuit, need to be scaled down for application in fifth-generation wireless communication networks. Due to the growing demands in memory and computational capacities of integrated circuits along with high processing and transmission data speed for next-generation, microelectronics will be replaced by nanoelectronics in the future. The concept of nanoscale network on chip system is expected to play an important role in the field of communication systems for designing new devices of ultra-high speed for long and short-range communication links, power efficient computing devices, high-density memory and logic, and ultrafast interconnects. This chapter focuses on the mechanism of tailoring, patterning, and manipulating optical signals using nanometer-scale structures that may play the role of lumped nanocircuit elements at optical domain when selected properly with tremendous promise for application for fifth-generation communication systems.

A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP

2007 ◽  
Vol 16 (01) ◽  
pp. 51-63
Author(s):  
CHI-CHOU KAO
Keyword(s):  
High Speed ◽  
Distribution Network ◽  
Clock Signal ◽  
Clock Distribution ◽  
Single Chip ◽  
New Approach ◽  
Flexibility Design ◽  
Clock Distribution Network ◽  
On Chip ◽  
High Flexibility

The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.

scholarly journals On-Chip Hardware Accelerator For DSP Applications

2019 ◽  
Vol 8 (3) ◽  
pp. 7534-7538
Keyword(s):  
High Speed ◽  
Multimedia Applications ◽  
Hardware Accelerator ◽  
Single Chip ◽  
Computing Systems ◽  
Processing Elements ◽  
Execution Speed ◽  
Computing Platforms ◽  
On Chip ◽  
Dsp Applications

High speed computing systems developed for multimedia streaming application demand high throughput and which can be achieved by designing hardware accelerators for data processing. This article presents new hardware accelerating platform comprised of heterogeneous multi core processing elements integrated on single chip FPGA. This kind of multi core platform can boost multimedia applications through parallel processing. The proposed multi core platform has been realized on FPGA and few DSP applications are executed on the processing elements of the platform to validate its performance. The performance of the proposed hardware accelerator has been compared with existing standard computing platforms frequently used for multimedia applications. The comparison shows that the proposed on-chip multi core accelerator has enhanced the execution speed of DSP applications while providing optimum throughput.

scholarly journals Design of Five Port Router for 3x3 Mesh Network Using Verilog

2021 ◽  
Vol 9 (VI) ◽  
pp. 5486-5492
Author(s):  
Rakshith Kumar
Keyword(s):  
Building Blocks ◽  
Network On Chip ◽  
Mesh Network ◽  
Single Chip ◽  
Fpga Design ◽  
Switched Network ◽  
Ip Cores ◽  
Store And Forward ◽  
On Chip ◽  
Parallel Connections

With technological advancements, a large number of intellectual property (IP) cores can be integrated into a single chip. As a result, communication between these cores is critical. Such communication is achieved using Network on Chip (NoC) technology. NoC is an on-chip packet-switched network with IP cores connected to the network via interfaces, and packets are sent to their destinations via a multi-chip routing path. A router is the essential component of the NoC architecture, it must be designed efficiently to build a competitive NoC architecture. Verilog is used to design the router which supports five parallel connections. It uses store and forward type of flow control, round-robin arbitration, and deterministic XY routing. The building blocks of the router are FIFO, arbiter, and crossbar. The proposed architecture of the five port router is targeted to the Spartan 6 XC6SLX45 FPGA design platform and simulated in Xilinx ISE 14.5 software.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

An all optical photonic crystal half adder suitable for optical processing applications

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Hamed Azhdari ◽  
Sahel Javahernia
Keyword(s):  
Photonic Crystal ◽  
Optical Waveguides ◽  
High Speed ◽  
Building Blocks ◽  
Optical Signal ◽  
Ring Resonators ◽  
Optical Processing ◽  
Nonlinear Photonic Crystal ◽  
Half Adder ◽  
All Optical

Abstract Increasing the speed of operation in all optical signal processing is very important. For reaching this goal one needs high speed optical devices. Optical half adders are one of the important building blocks required in optical processing. In this paper an optical half adder was proposed by combining nonlinear photonic crystal ring resonators with optical waveguides. Finite difference time domain method wase used for simulating the final structure. The simulation results confirmed that the rise time for the proposed structure is about 1 ps.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

scholarly journals 2D-3D integration of hexagonal boron nitride and a high-κ dielectric for ultrafast graphene-based electro-absorption modulators

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Hitesh Agarwal ◽  
Bernat Terrés ◽  
Lorenzo Orsini ◽  
Alberto Montanaro ◽  
Vito Sorianello ◽  
...  
Keyword(s):  
Boron Nitride ◽  
Hafnium Oxide ◽  
High Speed ◽  
Hexagonal Boron Nitride ◽  
Temperature Stability ◽  
Cost Effective ◽  
Fold Increase ◽  
Building Blocks ◽  
High Quality ◽  
New Device

AbstractElectro-absorption (EA) waveguide-coupled modulators are essential building blocks for on-chip optical communications. Compared to state-of-the-art silicon (Si) devices, graphene-based EA modulators promise smaller footprints, larger temperature stability, cost-effective integration and high speeds. However, combining high speed and large modulation efficiencies in a single graphene-based device has remained elusive so far. In this work, we overcome this fundamental trade-off by demonstrating the 2D-3D dielectric integration in a high-quality encapsulated graphene device. We integrated hafnium oxide (HfO2) and two-dimensional hexagonal boron nitride (hBN) within the insulating section of a double-layer (DL) graphene EA modulator. This combination of materials allows for a high-quality modulator device with high performances: a ~39 GHz bandwidth (BW) with a three-fold increase in modulation efficiency compared to previously reported high-speed modulators. This 2D-3D dielectric integration paves the way to a plethora of electronic and opto-electronic devices with enhanced performance and stability, while expanding the freedom for new device designs.

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