Multi-Valued PAM-N Data Transmission Using Double-Rate Tomlinson-Harashima Precoding

2019 ◽  
Vol 888 ◽  
pp. 59-65 ◽  
Author(s):  
Yosuke Iijima ◽  
Yasushi Yuminaka
Keyword(s):  
Data Transmission ◽  
Intersymbol Interference ◽  
Average Power ◽  
Strip Line ◽  
Eye Opening ◽  
Equalization Technique ◽  
Simulation Results

This paper presents an evaluation of double-rate Tomlinson-Harashima precoding in multi-valued PAM-N data transmission. In order to eliminate an intersymbol interference of interconnections in VLS system, Tomlinson-Harashima precoding (THP) is very useful for limiting the peak and average power of the transmitter. To expand the eye-opening at a receiver in multi-valued data transmission, we proposed a new equalization technique by using double-rate THP. In this paper, to evaluate the performance of the double-rate THP, we show the simulation results of the double-rate THP in various PAM-N data transmission on a micro-strip line.

scholarly journals Combined Detector with Retraining Data Sequence

2018 ◽  
Vol 15 (1) ◽  
pp. 47-50
Author(s):  
Muhanned AL-Rawi ◽  
Muaayed AL-Rawi
Keyword(s):  
Data Transmission ◽  
Intersymbol Interference ◽  
Communication Channels ◽  
Data Sequence ◽  
Channel Simulation ◽  
Simulation Results ◽  
Viterbi Detector ◽  
Using Data ◽  
Better Than

Abstract Two detectors are presented in this paper which are used to handle intersymbol interference introduced by the communication channels. These two detectors are based on combination of nonlinear equalizer and Viterbi detector. The first detector, which was previously developed, is named Combined Detector1(CDR1), while, the second detector, which is the contribution of this paper, is named Combined Detector-2(CDR2). CDR2 is similar to CDR1 but with retraining data sequence. These detectors are tested beside nonlinear equalizer using data transmission at 9.6kb/s over telephone channel. Simulation results show that the performance of CDR2 is better than the performance of CDR1 while the performance of CDR1 is better than the performance of nonlinear equalizer.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

A Small World Routing Protocol in Wireless Sensor Networks

2011 ◽  
Vol 474-476 ◽  
pp. 828-833
Author(s):  
Wen Jun Xu ◽  
Li Juan Sun ◽  
Jian Guo ◽  
Ru Chuan Wang
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Routing Protocol ◽  
Data Transmission ◽  
Small World ◽  
Wireless Sensor ◽  
Small World Network ◽  
Average Delay ◽  
Network Diameter ◽  
Simulation Results

In order to reduce the average path length of the wireless sensor networks (WSNs) and save the energy, in this paper, the concept of the small world is introduced into the routing designs of WSNs. So a new small world routing protocol (SWRP) is proposed. By adding a few short cut links, which are confined to a fraction of the network diameter, we construct a small world network. Then the protocol finds paths through recurrent propagations of weak and strong links. The simulation results indicate that SWRP reduces the energy consumption effectively and the average delay of the data transmission, which leads to prolong the lifetime of both the nodes and the network.

scholarly journals A Novel Hardware Security Architecture: PD-CRP(PUF Database & Challenge-Response Pair) Bloom Filter on Memristor Based PUF

2020 ◽  
Author(s):  
Jungwon Lee ◽  
Seoyeon Choi ◽  
Dayoung Kim ◽  
Yunyoung Choi ◽  
Wookyung Sun
Keyword(s):  
Data Transmission ◽  
Hardware Security ◽  
Bloom Filter ◽  
Transmission Error ◽  
Bloom Filters ◽  
Search Performance ◽  
Security Technology ◽  
Security Environment ◽  
Filter Size ◽  
Simulation Results

Because the development of the internet of things (IoT) requires technology that transfers information between objects without human intervention, the core of IoT security will be secure authentication between devices or between devices and servers. Software-based authentication may be a security vulnerability in IoT, but hardware-based security technology can provide a strong security environment. A physical unclonable functions (PUFs) are a hardware security element suitable for lightweight applications. PUFs can generate challenge-response pairs(CRPs) that cannot be controlled or predicted by utilizing inherent physical variations that occur in the manufacturing process. In particular, pulse width memristive PUF (PWM-PUF) improves security performance by applying different write pulse widths and bank structures. Bloom filter (BF) is probabilistic data structures that answer membership queries using small memories. Bloom filter can improve search performance and reduce memory usage and are used in areas such as networking, security, big data, and IoT. In this paper, we propose a structure that applies Bloom filters based on the PWM-PUF to reduce PUF data transmission errors. The proposed structure uses two different Bloom filter types that store different information and that are located in front of and behind the PWM-PUF, improving security by removing challenges from attacker access. Simulation results show that the proposed structure decreases the data transmission error rate and reuse rate as the Bloom filter size increases, the simulation results also show that the proposed structure improves PWM-PUF security with a very small Bloom filter memory.

scholarly journals 2 Performance Evaluation of Code Division Multiple Access (CDMA) in terms of Power Measurement and Reduction

2011 ◽  
Vol 1 (1) ◽  
pp. 4
Author(s):  
Syed Rizwan-ul- Hasan ◽  
Shakil Ahmed
Keyword(s):  
Performance Evaluation ◽  
Code Division Multiple Access ◽  
Multiple Access ◽  
Average Power ◽  
Power Measurement ◽  
Cdma System ◽  
Power Ratio ◽  
Ratio Measurement ◽  
Simulation Results ◽  
Code Division Multiple

 In this research paper the performance of the CDMA system has been analyzed with respect to PAPR (Peak to Average Power Ratio) measurement and its reduction. Simulation results verify that high peaks degrade the performance of CDMA, application of codes reduced high peaks and PAPR is a good measure for CDMA.

scholarly journals Optimized Adaptive Huffmann Coding For Paper Reduction in OFDM Systems

2013 ◽  
Vol 2 (04) ◽  
pp. 13-18
Author(s):  
Dr. Atul Suryavanshi
Keyword(s):  
Average Power ◽  
High Peak ◽  
Huffman Coding ◽  
Power Ratio ◽  
Ofdm Systems ◽  
Main Defect ◽  
Simulation Results

The main defect of OFDM systems is its high peak-to-average power ratio (PAPR). To decrease PAPR, Adaptive Huffman coding is essential. Encoding is transferred by two encoding techniques Huffman coding and Adaptive Huffman coding at the transmitter side. Mapping is done by QAM 16 and PSK 16.The PAPR results of Huffman and adaptive Huffman coding with QAM 16 and PSK 16 is compared. Simulation results shows that the Adaptive Huffman coding along with QAM 16 produces fruitful results in comparison with Huffman coding and adaptive Huffman coding with PSK 16.

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

scholarly journals Simulation and Measurement Studies of The Vdes System’s Terrestrial Component

2019 ◽  
Vol 26 (1) ◽  
pp. 95-106 ◽  
Author(s):  
Krzysztof Bronk ◽  
Patryk Koncicki ◽  
Adam Lipka ◽  
Dominik Rutkowski ◽  
Błażej Wereszko
Keyword(s):  
Data Transmission ◽  
Data Exchange ◽  
Technical Information ◽  
Theoretical Data ◽  
Current Version ◽  
Coding Gain ◽  
Exchange System ◽  
Measurement Results ◽  
Simulation Results ◽  
Theoretical Results

Abstract In the paper, the measurement and simulation results of the VDES (VHF Data Exchange System) terrestrial component are discussed. It is anticipated that VDES will be one of the major solutions for maritime communications in the VHF band and its performance will be sufficient to fulfill the requirements of the e-navigation applications. The process of the VDES standardization (ITU R, IALA) has not been officially completed yet, but substantial amount of technical information about the future system’s terrestrial component (VDE-TER) is already available. The paper is divided into three general parts: (a) theoretical presentation of the system’s physical layer and the radio channels applicable to VDES, (b) simulation results (BER, BLER, channel delay between two propagation paths and its influence on bit rates) and (c) measurement results (useful ranges, BER). It turned out that in real maritime conditions, the VDES system can offer ranges between 25 and 38 km for the configurations assumed during the measurement campaign. Those results are generally compliant with the theoretical data in the line-of-sight conditions. In the NLOS scenarios, where fading becomes the dominant phenomenon, the discrepancies between the measurements and the theoretical results were more significant. The obtained results confirmed that VDES provides a large coding gain, which significantly improves the performance of data transmission and increases the bit rate compared to the existing maritime radiocommunication solutions. It should be noted that the results presented in the article were used by the IALA while developing the current version of the VDES specification.

Comparison of NRZ and 4-PAM Coding for High-Speed VLSI Data Transmission

2015 ◽  
Vol 643 ◽  
pp. 141-147
Author(s):  
Yasushi Yuminaka ◽  
Yuuki Takada
Keyword(s):  
Data Transmission ◽  
High Frequency ◽  
High Speed ◽  
Strip Line ◽  
Frequency Channel ◽  
Test Board ◽  
Crucial Problem ◽  
Vlsi System ◽  
High Speed Data ◽  
Speed Data Transmission

As the Required Data Rate for VLSI System Communication Increases, Channel Bandwidthlimitation Becomes a Crucial Problem as High-Frequency Channel Loss Degrades the Transmission Performance.In this Paper, we Compare Non-Return-to-Zero (NRZ) Binary and 4-PAM (pulse Amplitudemodulation) Coding Techniques for High-Speed Data Transmission by Fabricating a Test Board of a Microstripline. by Extracting the Micro-Strip Line Parameters, we Carry out Co-Simulations to Evaluate Spectrallyefficient Coding for High-Speed Data Transmission.We Consider the Conditions for which 4-Pamsignaling Provides an Advantage over NRZ Signaling from the Viewpoint of Channel Profiles.

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