scholarly journals Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits

2005 ◽  
Vol 3 ◽  
pp. 281-285 ◽  
Author(s):  
Ph. Teichmann ◽  
J. Fischer ◽  
E. Amirante ◽  
St. Henzler ◽  
A. Bargagli-Stoffi ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Power Supply ◽  
New Technologies ◽  
Clock Cycle ◽  
Cmos Process ◽  
Gate Leakage ◽  
Clock Period ◽  
Leakage Currents ◽  
Additional Energy ◽  
Adiabatic Logic

Abstract. Losses due to gate-leakage-currents become more dominant in new technologies as gate leakage currents increase exponentially with decreasing gate oxide thickness. The most promising Adiabatic Logic (AL) families use a clocked power supply with four states. Hence, the full VDD voltage drops over an AL gate only for a quarter of the clock cycle, causing a full gate leakage only for a quarter of the clock period. The rising and falling ramps of the clocked power supply lead to an additional energy consumption by gate leakage. This energy is smaller than the fraction caused by the constant VDD drop, because the gate leakage exponentially depends on the voltage across the oxide. To obtain smaller energy consumption, Improved Adiabatic Logic (IAL) has been introduced. IAL swaps all n- and p-channel transistors. The logic blocks are built of p-channel devices which show gate tunneling currents significantly smaller than in n-channel devices. Using IAL instead of conventional AL allows an additional reduction of the energy consumption caused by gate leakage. Simulations based on a 90nm CMOS process show a lowering in gate leakage energy consumption for AL by a factor of 1.5 compared to static CMOS. For IAL the factor is up to 4. The achievable reduction varies depending on the considered AL family and the complexity of the gate.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 180-185 ◽  
Author(s):  
Jian Ping Hu ◽  
Yu Zhang
Keyword(s):  
Energy Savings ◽  
Cmos Process ◽  
Gate Length ◽  
Mos Transistors ◽  
Traffic Light ◽  
Leakage Currents ◽  
Two Phase ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
The One

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

Naval Energy Management System

2020 ◽  
Vol 26 (3) ◽  
pp. 20-25
Author(s):  
Laurențiu Bogdan Asalomia ◽  
Gheorghe Samoilescu
Keyword(s):  
Energy Consumption ◽  
Power Systems ◽  
New Technologies ◽  
Integrated Navigation ◽  
Integrated Navigation System ◽  
Efficient Management ◽  
Reduce Energy Consumption ◽  
Energy Efficiency Design Index ◽  
Green Ship

AbstractThe paper analyses the role of control and monitoring of electro-energetic equipment in order to reduce operational costs, increase profits and reduce carbon emissions. The role of SCADA and EcoStruxure Power systems is presented and analysed taking into account the energy consumption and its savings. The paper presents practical and modern solutions to reduce energy consumption by up to 53%, mass by up to 47% and increase the life of the equipment by adjusting the electrical parameters. The Integrated Navigation System has allowed an automatic control and an efficient management. For ships, the implementation of an energy efficiency design index and new technologies was required for the GREEN SHIP project.

scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

scholarly journals In-Situ Synthesis of TiO2@GO Nanosheets for Polymers Degradation in a Natural Environment

Polymers ◽  
2021 ◽  
Vol 13 (13) ◽  
pp. 2158
Author(s):  
Yueqin Shi ◽  
Zhanyang Yu ◽  
Zhengjun Li ◽  
Xiaodong Zhao ◽  
Yongjun Yuan
Keyword(s):  
Natural Environment ◽  
New Technologies ◽  
Separation Efficiency ◽  
Basic Mechanism ◽  
Chemical Degradation ◽  
Natural Environments ◽  
Additional Energy ◽  
Photogenerated Electrons ◽  
Main Components

Plastic photodegradation naturally takes 300–500 years, and their chemical degradation typically needs additional energy or causes secondary pollution. The main components of global plastic are polymers. Hence, new technologies are urgently required for the effective decomposition of the polymers in natural environments, which lays the foundation for this study on future plastic degradation. This study synthesizes the in-situ growth of TiO2 at graphene oxide (GO) matrix to form the TiO2@GO photocatalyst, and studies its application in conjugated polymers’ photodegradation. The photodegradation process could be probed by UV-vis absorption originating from the conjugated backbone of polymers. We have found that the complete decomposition of various polymers in a natural environment by employing the photocatalyst TiO2@GO within 12 days. It is obvious that the TiO2@GO shows a higher photocatalyst activity than the TiO2, due to the higher crystallinity morphology and smaller size of TiO2, and the faster transmission of photogenerated electrons from TiO2 to GO. The stronger fluorescence (FL) intensity of TiO2@GO compared to TiO2 at the terephthalic acid aqueous solution indicates that more hydroxyl radicals (•OH) are produced for TiO2@GO. This further confirms that the GO could effectively decrease the generation of recombination centers, enhance the separation efficiency of photoinduced electrons and holes, and increase the photocatalytic activity of TiO2@GO. This work establishes the underlying basic mechanism of polymers photodegradation, which might open new avenues for simultaneously addressing the white pollution crisis in a natural environment.

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

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