The Design and Implementation of a High-Speed Parallel AES Crypto-Chip

2012 ◽  
Vol 468-471 ◽  
pp. 1721-1725 ◽  
Author(s):  
Jun Yang ◽  
Wei Ping Zhang ◽  
Ping Ping Shu ◽  
Xiao Jun Wang ◽  
Ga Zhao ◽  
...  
Keyword(s):  
High Speed ◽  
Language Use ◽  
Processing Unit ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Time Requirements ◽  
Hardware Description ◽  
Network Transmission ◽  
Encryption Decryption

This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The design goal is to optimize the hardware structure and improve the throughput, S-box design and parallel processing structure. Compared with traditional AES crypto-chip has faster rate with encryption and less consumption of resources advantages. This design adopts VHDL hardware description language, use Quartus II 8.0 for the synthesis and routing, and this processing unit is packaged an independent IP core, attached to the Altera provided the Nios II system, finally download and test validation on the DE2 development platform.

IP Core Design of 8253 Based on Quartus II

2013 ◽  
Vol 380-384 ◽  
pp. 2941-2944
Author(s):  
Hai Yan Zhang
Keyword(s):  
Software Development ◽  
Hardware Description Language ◽  
Logic Design ◽  
Ip Core ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Hardware Description ◽  
Gate Array

Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

scholarly journals Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic

2014 ◽  
Vol 3 (03) ◽  
pp. 01-06
Author(s):  
Mrs. Leena Rathi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Research Work ◽  
Processing Unit ◽  
Central Processing ◽  
High Speeds ◽  
Quartus Ii ◽  
Hardware Description ◽  
Digital Processor ◽  
Very High

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.     

Design and Simulation on High Speed FFT Processor in Radar Signal Processing

2012 ◽  
Vol 461 ◽  
pp. 333-337 ◽  
Author(s):  
Shun Xin Li ◽  
Yu Fan Mo
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
Hardware Description Language ◽  
Radar Signal ◽  
Radar Signal Processing ◽  
Simulation Tool ◽  
Description Language ◽  
Fft Processor ◽  
Quartus Ii ◽  
Hardware Description

Based on the high-speed, real-time and high precision of radar signal processing, FFT arithmetic is utilized in the radar signal processing and FFT processor is designed and implemented. The proposed processor adopts radix-2 FFT algorithm. FFT computing based on FPGA has the advantages of high speed, less resource occupancy, easy algorithm and convenient system debugging and implementation. It is composed employing VHDL as hardware description language, FPGA as the logic controller, Quartus II as designing and synthesis simulation tool. The simulation results indicated FFT processor approached the request of the radar signal processing and it is suitable for the application of high-speed signal processing

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

A modeling method of algorithm-hardware based on SysML

2021 ◽  
Author(s):  
Liu Yue ◽  
Zhao Chun ◽  
Zhang Lin
Keyword(s):  
Graphical Models ◽  
Integrated Circuit ◽  
High Speed ◽  
System Modeling ◽  
Modeling Method ◽  
Description Language ◽  
Hardware Description ◽  
Circuit And System ◽  
Graphical System ◽  
Hardware Circuit

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

Implementation of CRC by Using FPGA in Data Communication

2013 ◽  
Vol 325-326 ◽  
pp. 1805-1808
Author(s):  
Lie Wang ◽  
Yi Jie Wang
Keyword(s):  
Hardware Implementation ◽  
Data Communication ◽  
Communication Process ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Communication Structure ◽  
Development Platform ◽  
Hardware Description ◽  
Analyze Data

By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

Implementation of High Speed Self Switching Frequency Agile RADAR

2013 ◽  
Vol 3 (1) ◽  
pp. 11
Author(s):  
K Jansi Lakshmi ◽  
K Surya Narayana Reddy
Keyword(s):  
High Speed ◽  
Switching Frequency ◽  
Frequency Diversity ◽  
Description Language ◽  
General Application ◽  
Frequency Agile ◽  
On Line ◽  
Hardware Description ◽  
Effective Function ◽  
Self Adaptive

<div class="WordSection1"><p><strong><a href="mailto:[email protected]"></a></strong></p></div><strong> </strong>The radar has to resist diversified jamming; High Speed self-adaptive frequency   agility   is   an   important   and   effective function  for radars to resist jamming.  The procedure to achieve this function are described, and the function is realized with FPGA using Hardware description  Language, the validity is proved by on- line sampling and simulation. The High speed self-adaptive frequency agility module can analyze the type of jamming to select  transmitting  frequency  to avoid the frequencies which have interference, under frequency       diversity  and  fixed  frequency, respectively. The   general   application   on   a   searching   radar shows that the module has good real-time and anti- jamming capacity.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Oscar Montiel-Ross ◽  
Jorge Quiñones ◽  
Roberto Sepúlveda
Keyword(s):  
Parallel Programming ◽  
High Speed ◽  
High Performance ◽  
Hardware Description Language ◽  
System Response ◽  
Description Language ◽  
Tuning Method ◽  
Hardware Description ◽  
Ip Cores ◽  
Fuzzy Pd

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

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