BiCMOS Flip-Flop Design Based on NPN-NPN Feedback Driver Circuits

2013 ◽  
Vol 712-715 ◽  
pp. 1826-1829
Author(s):  
Mao Qun Yao ◽  
Li Bin Zhang ◽  
Han Neng Ye
Keyword(s):  
General Structure ◽  
Sequential Circuits ◽  
Logical Function ◽  
Flip Flop ◽  
Transmission Gate ◽  
Driver Circuit ◽  
Hspice Simulation

based on the analyzing the characteristic of BiCMOS circuits and theory of transmission voltage-switches, we proposed a general structure of binary BiCMOS circuit based on NPN-NPN feedback driver circuit. Then we designed binary BiCMOS master-slave JK flip-flop circuit and transmission gate D flip-flop circuit base on the general structure of NPN-NPN feedback driver circuit. With using HSPICE simulation, the results show that the circuits have the correct logical function. The proposed driver circuits can be used in the design of BiCMOS sequential circuits.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

2019 ◽  
Vol 29 (08) ◽  
pp. 2050123 ◽  
Author(s):  
Neethu Anna Sabu ◽  
K. Batri
Keyword(s):  
Vlsi Design ◽  
Cmos Technology ◽  
Flip Flop ◽  
Circuit Performance ◽  
Power Efficient ◽  
Transmission Gate ◽  
Double Edge ◽  
Speed Performance ◽  
Layout Area ◽  
Power Delay Product

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

Design of a novel quantum reversible ternary up-counter

2015 ◽  
Vol 13 (05) ◽  
pp. 1550038 ◽  
Author(s):  
Pouran Houshmand ◽  
Majid Haghparast
Keyword(s):  
Power Dissipation ◽  
Reversible Logic ◽  
Sequential Circuits ◽  
Utilization Rate ◽  
Time And Space ◽  
Space Utilization ◽  
Flip Flop ◽  
New Approach ◽  
Combinational And Sequential Circuits ◽  
Better Than

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.

scholarly journals Compact QCA based JK Flip-Flop for Digital System

2019 ◽  
Vol 8 (12) ◽  
pp. 3182-3185 ◽  
Keyword(s):  
Cellular Automaton ◽  
Cmos Technology ◽  
Sequential Circuits ◽  
Low Energy ◽  
High Rate ◽  
Combinational Circuits ◽  
Flip Flop ◽  
Binary Information ◽  
Cad Tool ◽  
Mos Circuits

Considering the roadmap of silicon, the high rate of shrinkage in dimensions of typical MOS circuits, genuine difficulties endanger this innovation. A quantum-dot cellular automaton (QCA) is an outstanding and conceivable answer for substitution of CMOS technology. Sequential circuits contain combinational circuits and memory elements which store binary information. Latches and Flip-flop circuits are the basic components of computerized circuits, along these lines. The area and energy of the sequential circuits has to be minimal for speed applications. Traditional implementation of JK flip-flop circuits requires more cells and consumes more energy. This paper proposes a compact and low energy JK Flip-flop, designed in CAD tool, QCADesigner. Analysis of energy was performed using the CAD tool, QCADesigner-E. The experimental results obtained in the proposed paper demonstrate the reduction in the cell count which in turn brings down the complexity of the circuit when compared to the reference QCA based JK Flip-flop circuits and it also shows a reduction in energy and area.

scholarly journals A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
Transient Response ◽  
High Performance ◽  
Cmos Technology ◽  
Flip Flop ◽  
Parasitic Extraction ◽  
Transmission Gate ◽  
Modern Process ◽  
Capacitive Load ◽  
Area Product

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

scholarly journals Digital System Design

2021 ◽  
Author(s):  
Janani Rajaraman
Keyword(s):  
System Design ◽  
Full Adder ◽  
Sequential Circuits ◽  
Digital System ◽  
Digital Systems ◽  
Combinational Circuits ◽  
Boolean Expression ◽  
Flip Flop ◽  
Half Adder ◽  
Digital System Design

The main objective of this chapter is to study and design various combinational circuits like Verification of Boolean Expression, Multiplexer, Demultiplexer Circuits, Code Converters circuits using LabVIEW tools. This chapter will make the user more comfortable towards learning of Design of Digital Systems. The various types of Boolean Expressions like SOP and POS, Combinational circuits like Adder circuit (Half adder and full adder), Subtractor circuit (Half Subtractor, Full Subtractor), some code converters like Binary to Gray and Gray to Binary, BCD to Gray and Gray to BCD and also Sequential circuits with D flip flop is also being carried out using this LabVIEW.

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