Effect of Surface Orientation and Off-Angle on Surface Roughness and Electrical Properties of p-Type Impurity Implanted 4H-SiC Substrate after High Temperature Annealing

2006 ◽  
Vol 527-529 ◽  
pp. 835-838 ◽  
Author(s):  
Akimasa Kinoshita ◽  
Makoto Katou ◽  
Miwa Kawasaki ◽  
Kazutoshi Kojima ◽  
Kenji Fukuda ◽  
...  
Keyword(s):  
Surface Roughness ◽  
High Temperature ◽  
Annealing Temperature ◽  
Surface Orientation ◽  
Free Carrier ◽  
Root Mean Square Roughness ◽  
Mean Square ◽  
High Temperature Annealing ◽  
P Type ◽  
Effect Of Surface

We investigate the effect of surface orientation and off-angle for Al-implanted 4H-SiC samples after high temperature annealing. The samples are obtained from a 4H-SiC (0001) substrate 8° off-angled (Si-face 8°off), and (000-1) substrates 8° (C-face 8°off), 4° (C-face 4°off) and less than 1° off-angled (C-face ~1°off). An n-type epitaxial layer is deposited on all substrates. Multiple implantations of Al+ (30~200keV) are carried out at 600°C. The total dose is 8.6 × 1015 cm-2. The Al-implanted samples are annealed in Ar ambient at 1580°C, 1700°C and 1800°C for 30s using the hybrid super rapid thermal annealing (HS-RTA) equipment. In this study, sheet resistance (Rs), free carrier concentration (Ns), Hall mobility (μ) and root-mean square roughness (Rrms) are used to evaluate the Al-implanted samples after high temperature annealing. Rs for all Al-implanted samples after annealing at 1800°C for 30s is around 18k/. Rrms for the Al-implanted C-face samples after annealing at 1800°C increases with increasing off-angle. Rrms for the Al-implanted Si-face 8°off sample after annealing increases with annealing temperature. Rrms for the C-face ~1°off Al-implanted sample after annealing at 1800°C is lower than that for the Si-face 8°off Al-implanted sample after annealing at 1700°C, moreover Rs for the C-face ~1°off sample after annealing at 1800°C is about 10% of that for the Si-face 8°off Al-implanted sample after annealing at 1700°C. It is shown that the C-face ~1°off sample is useful to fabricate a p+ region with low Rs and low Rrms. If C-face 4H-SiC is used to fabricate devices, devices made on C-face 4H-SiC with low off angle are expected to decrease any problems caused by increase of surface roughness after high temperature annealing (~1800°C).

scholarly journals Effect of High-Temperature Annealing on Ion-Implanted Silicon Solar Cells

2012 ◽  
Vol 2012 ◽  
pp. 1-6 ◽  
Author(s):  
Hyunpil Boo ◽  
Jong-Han Lee ◽  
Min Gu Kang ◽  
KyungDong Lee ◽  
Seongtak Kim ◽  
...  
Keyword(s):  
Solar Cells ◽  
High Temperature ◽  
Annealing Temperature ◽  
Silicon Solar Cells ◽  
High Temperature Annealing ◽  
Abrupt Decrease ◽  
Simulation Based ◽  
P Type ◽  
Pc1d Simulation ◽  
Ion Implanted

P-type and n-type wafers were implanted with phosphorus and boron, respectively, for emitter formation and were annealed subsequently at 950∼1050∘Cfor 30∼90 min for activation. Boron emitters were activated at1000∘Cor higher, while phosphorus emitters were activated at950∘C. QSSPC measurements show that the impliedVocof boron emitters increases about 15 mV and theJ01decreases by deep junction annealing even after the activation due to the reduced recombination in the emitter. However, for phosphorus emitters the impliedVocdecreases from 622 mV to 560 mV and theJ01increases with deep junction annealing. This is due to the abrupt decrease in the bulk lifetime of the p-type wafer itself from 178 μs to 14 μs. PC1D simulation based on these results shows that, for p-type implanted solar cells, increasing the annealing temperature and time abruptly decreases the efficiency (Δηabs=−1.3%), while, for n-type implanted solar cells, deep junction annealing increases the efficiency andVoc, especially (Δηabs=+0.4%) for backside emitter solar cells.

scholarly journals Влияние температуры отжига на электрически активные центры в кремнии, имплантированном ионами германия

2019 ◽  
Vol 53 (2) ◽  
pp. 161
Author(s):  
Н.А. Соболев ◽  
О.В. Александров ◽  
В.И. Сахаров ◽  
И.Т. Серенков ◽  
Е.И. Шек ◽  
...  
Keyword(s):  
High Temperature ◽  
Single Crystal ◽  
Annealing Temperature ◽  
Single Crystal Silicon ◽  
High Temperature Annealing ◽  
Crystal Silicon ◽  
Type Silicon ◽  
Special Distribution ◽  
P Type

AbstractThe implantation of Czochralski-grown p -type silicon with 1-MeV germanium ions at a dose of 2 . 5 × 10^14 cm^–2 does not lead to the amorphization of single-crystal silicon. Under subsequent high-temperature annealing, electrically active acceptor centers are transformed. Their concentration and special distribution depend on the annealing temperature. The possible factors determining how these centers are formed are discussed.

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Impact of CF4 Plasma Treatment on the Surface Roughness of Ion Implanted SiC Induced by High Temperature Annealing

2010 ◽  
Vol 645-648 ◽  
pp. 783-786
Author(s):  
Tatsunori Sugimoto ◽  
Masataka Satoh ◽  
Tohru Nakamura ◽  
K. Mashimo ◽  
Hiroshi Doi ◽  
...  
Keyword(s):  
Surface Roughness ◽  
High Temperature ◽  
Energy Range ◽  
Plasma Treatment ◽  
Surface Roughening ◽  
High Temperature Annealing ◽  
Small Surface ◽  
Step Structure ◽  
The Impact ◽  
Ion Implanted

The impact of CF4 plasma treatment on the surface roughening of SiC has been investigated for N ion implanted SiC(0001) which is implanted with the energy range from 15 to 120 keV at a dose of 9.2 x 1014/cm2. The N ion implanted sample, which is processed by CF4 plasma, shows small surface roughness of 1.6 nm after annealing at 1700 oC for 10 min, while the sample without CF4 plasma treatment shows the large surface roughness (6.6nm) and micro step structure. XPS measurements reveals that CF4 plasma treatment is effective to dissolved the residual oxide on the surface of SiC which is not removed by BHF acid of SiO2 layer on SiC. It is strongly suggested that the formation of micro step structure with the increase of the surface roughness is promoted by the residual oxide such as SiCOx, on SiC.

PHASE EVOLUTION AND MAGNETIC PROPERTIES OF FEPT-PTTE2 NANORODS

2009 ◽  
Vol 23 (17) ◽  
pp. 3573-3578
Author(s):  
QINGYU YAN ◽  
AIDONG LI
Keyword(s):  
Magnetic Properties ◽  
Phase Transformation ◽  
High Temperature ◽  
Annealing Temperature ◽  
Phase Evolution ◽  
Polyol Process ◽  
Phase Ratio ◽  
High Temperature Annealing ◽  
Two Phase

FePt - PtTe 2 two phase nanorods have been produced by a polyol process. The shape and magnetic properties of two phase nanorods with different phase ratio are investigated. L10 phase transformation of FePt in the nanorods has been accomplished at annealing temperature as low as 400 °C with Hc above 500mT. High temperature annealing causes the disintegration of the nanorods due the melting/evaporation of Te element.

Instabilities and Point Defects at Step-Free Si(001) and (111) Terraces During High Temperature Annealing

1999 ◽  
Vol 587 ◽  
Author(s):  
Doohan Lee ◽  
Jack M. Blakely
Keyword(s):  
High Temperature ◽  
Point Defect ◽  
Point Defects ◽  
Strain Energy ◽  
Annealing Temperature ◽  
Small Islands ◽  
High Temperature Annealing ◽  
Atomic Steps ◽  
The Stability

AbstractIn this paper we describe observations on the stability of extremely large Si(001) and (111) terraces that are formed by a technique described previously. Following annealing at high temperature and quenching, a series of concentric pits of monoatomic depth are observed with spacing between successive pits of the order of several microns; pits do not form on (111) until the terraces get extremely large. The occurrence of small islands or small pits on the terraces of quenched samples gives information on the majority point defect at the annealing temperature. On (001) samples that are slowly cooled from the annealing temperature, it is observed that pairs of atomic steps have formed on the large terrace; we believe that these result from the tendency of the surface to minimize the strain energy associated with the (2 × 1) reconstruction.

Suppression of SiC surface roughening during high-temperature annealing by atmospheric control using purified Ar gas

2010 ◽  
Vol 25 (4) ◽  
pp. 708-710 ◽  
Author(s):  
Atsushi Ogura ◽  
Daisuke Kosemura ◽  
Shingo Kinoshita
Keyword(s):  
Surface Roughness ◽  
High Temperature ◽  
Surface Roughening ◽  
Annealing Atmosphere ◽  
High Temperature Annealing ◽  
Force Microscopy ◽  
Atomic Force ◽  
Before And After ◽  
Furnace Tube ◽  
Ar Gas

4H-silicon carbide (SiC) wafers were annealed at 1300 and 1600 °C for 30 min and 60 min in a conventional and purified Ar atmosphere. The surface roughness before and after annealing was evaluated by atomic force microscopy. The surface roughness before annealing was approximately 2.37 nm in root mean square. The roughness, after annealing for 30 min at 1300 and 1600 °C in a conventional Ar furnace, was increased to 4.53 and 14.9 nm, respectively. The roughness, after annealing for 60 min, was 5.01 and 19.1 nm, respectively. In this study, the G3 grade Ar gas (99.999%) was supplied in the conventional furnace tube. When the Ar gas was purified to an impurity concentration of less than 1 ppb, and it was supplied in the leak-tight furnace tube, the roughness after 30-min annealing improved 4.27 and 6.93 nm at 1300 and 1600 °C, respectively. The roughness after 60-min annealing was also reduced to 3.54 and 9.28 nm, respectively. We assume that a significant reduction of H2O concentration in the annealing atmosphere might play an important role in suppressing surface roughening of SiC during high-temperature annealing.

Correlation Study of Morphology, Electrical Activation and Contact formation of Ion Implanted 4H-SiC

2009 ◽  
Vol 156-158 ◽  
pp. 493-498
Author(s):  
Ming Hung Weng ◽  
Fabrizio Roccaforte ◽  
Filippo Giannazzo ◽  
Salvatore di Franco ◽  
Corrado Bongiorno ◽  
...  
Keyword(s):  
High Temperature ◽  
Surface Morphology ◽  
Electrical Activation ◽  
Structural Defects ◽  
High Resistivity ◽  
Al Alloy ◽  
High Temperature Annealing ◽  
Capping Layer ◽  
P Type ◽  
Ion Implanted

This paper reports a detailed study of the electrical activation and the surface morphology of 4H-SiC implanted with different doping ions (P for n-type doping and Al for p-type doping) and annealed at high temperature (1650–1700 °C) under different surface conditions (with or without a graphite capping layer). The combined use of atomic force microscopy (AFM), transmission electron microscopy (TEM), and scanning capacitance microscopy (SCM) allowed to clarify the crucial role played by the implant damage both in evolution of 4H-SiC surface roughness and in the electrical activation of dopants after annealing. The high density of broken bonds by the implant makes surface atoms highly mobile and a peculiar step bunching on the surface is formed during high temperature annealing. This roughness can be minimized by using a capping layer. Furthermore, residual lattice defects or precipitates were found in high dose implanted layers even after high temperature annealing. Those defects adversely affect the electrical activation, especially in the case of Al implantation. Finally, the electrical properties of Ni and Ti/Al alloy contacts on n-type and p-type implanted regions of 4H-SiC were studied. Ohmic behavior was observed for contacts on the P implanted area, whilst high resistivity was obtained in the Al implanted layer. Results showed a correlation of the electrical behavior of contacts with surface morphology, electrical activation and structural defects in ion-implanted, particularly, Al doped layer of 4H-SiC.

Mitigation of BPD by Pre-Epigrowth High Temperature Substrate Annealing

2016 ◽  
Vol 858 ◽  
pp. 233-236 ◽  
Author(s):  
Nadeemullah A. Mahadik ◽  
Robert E. Stahlbush ◽  
Eugene A. Imhoff ◽  
M.J. Tadjer ◽  
G.E. Ruland ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Atomic Force Microscopy ◽  
High Temperature ◽  
Surface Morphology ◽  
Substrate Surface ◽  
High Temperature Annealing ◽  
Force Microscopy ◽  
Atomic Force ◽  
Substrate Annealing ◽  
Edge Dislocations

Basal Plane Dislocations (BPD) intersecting the SiC substrate surface were converted to threading edge dislocations (TED) by high temperature annealing of the substrates in the temperature range of 1750 °C – 1950 °C. Successively, epitaxial growth on annealed as well as non-annealed samples was performed, concurrently, to investigate the effect of the substrate annealing on BPD mitigation in the epilayers. For the 1950 °C/10min anneal, a 3x reduction in BPD density was observed. Additionally, surface roughness measured using atomic force microscopy revealed no degradation in surface morphology of the grown epilayers after annealing.

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