Pretreatment of Blind Via Holes before Ni/Au and Cu Plating Applied with Atmospheric Pressure Plasma Jet

2005 ◽  
Vol 2 (3) ◽  
pp. 189-196 ◽  
Author(s):  
Yasushi Sawada ◽  
Keiichi Yamazaki ◽  
Noriyuki Taguchi ◽  
Tetsuji Shibata

The effectiveness of atmospheric pressure (AP) plasma preprocessing before Ni/Au or Cu plating has been examined by applying it to a build-up printed circuit board (FR-4 grade) and polyimide-based flexible circuit film, both with blind via-holes (BVHs). The AP plasma applied with a dielectric barrier discharge is generated inside a 56 mm wide quartz vessel by an RF power generator using Ar-O2 gas mixture. One side of the vessel is open and the plasma jet is blown on the sample substrate transported 5 mm downward from the outlet of the vessel. The deposit failure rate of Ni/Au electroless deposit to 50 μm-diameter BVHs formed on a photo resist on the printed circuit board is 12.5% without preprocessing but is decreased to 0% after applying the AP plasma processing. As for 50 μm-diameter BVHs formed with a YAG laser on a polyimide-based flexible circuit film, the bump formation using electrolytic copper plating fails without preprocessing, but a 100% bump formation rate is achieved after applying AP plasma processing. It is presumed that the AP plasma processing improves the wetting property of the BVH walls and allows the plating solution to uniformly cover the entire wall surfaces without generating bubbles. The removal of organic substances attached to the BVH bottom surface also helps to improve the adherence of metal plating.

Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.


2004 ◽  
Vol 1 (2) ◽  
pp. 95-101
Author(s):  
Yu Xiaoling ◽  
Xiong Wei ◽  
Zhou Wei ◽  
Feng Quanke

In a hybrid integrated power electronic module (IPEM) for medium power converter, when packaged with power circuit closely, the driver & protection circuit is affected seriously by heat generated from power chips in the power circuit. Thermal simulation results of the module show that the thermal resistance between the power chip and the bottom surface of substrate is 0.24 °C/W. Experimental results reveal that the highest temperature on the driver & protection printed circuit board (PCB) is over 70 °C when the power chip temperature reaches 93 °C. Therefore, an air gap is sandwiched between the power circuit and the driver & protection PCB to insulate the heat transferred from the former to the latter. Measuring results show that the air gap weakens the thermal effect of power circuit on the driver & protection PCB, and the highest temperature on the PCB decreases while the thickness of air gap increases. If the thickness of air gap increases to certain value, the highest temperature on the driver & protection PCB can be controlled below 70 °C when the power chip temperature reaches 125 °C.


2010 ◽  
Vol 2010.47 (0) ◽  
pp. 129-130
Author(s):  
Sadakazu TAKAKUWA ◽  
Masaru ISHIZUKA ◽  
Shinji NAKAGAWA ◽  
Tomoyuki HATAKEYAMA

2010 ◽  
Vol 7 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Zhou Zeng ◽  
Zhuang Li ◽  
Zuoyong Zheng

This paper investigates methodologies for locating and identifying the components on a printed circuit board (PCB) used for surface mount device inspection. The proposed scheme consists of two stages: solder joint extraction and protective coating extraction. Solder joints are extracted by first detecting all the highlight areas, and then recognizing and removing the invalid highlight areas which are mainly markings and via-holes. We sum up three color distribution features. And the invalid highlight areas are recognized and removed by comparing the features of the target objects and the reference objects. The sequence of color distribution as a new clue has been applied to clustering solder joints. Each protective coating is extracted by the positions of the clustered solder joints. Experimental results show that the proposed method can extract most of components effectively.


Sensors ◽  
2019 ◽  
Vol 19 (22) ◽  
pp. 4939 ◽  
Author(s):  
Antonio Alex-Amor ◽  
Javier Moreno-Núñez ◽  
José M. Fernández-González ◽  
Pablo Padilla ◽  
Jaime Esteban

This work presents some accurate guidelines for the design of rectifier circuits in radiofrequency (RF) energy harvesting. New light is shed on the design process, paying special attention to the nonlinearity of the circuits and the modeling of the parasitic elements. Two different configurations are tested: a Cockcroft–Walton multiplier and a half-wave rectifier. Several combinations of diodes, capacitors, inductors and loads were studied. Furthermore, the parasitics that are part of the circuits were modeled. Thus, the most harmful parasitics were identified and studied in depth in order to improve the conversion efficiency and enhance the performance of self-sustaining sensing systems. The experimental results show that the parasitics associated with the diode package and the via holes in the PCB (Printed Circuit Board) can leave the circuits inoperative. As an example, the rectifier efficiency is below 5% without considering the influence of the parasitics. On the other hand, it increases to over 30% in both circuits after considering them, twice the value of typical passive rectifiers.


2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.


Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.


Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.


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