Manufacturing Substrates with Embedded Passives

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002011-002050
Author(s):  
Rabindra N. Das ◽  
Konstantinos I. Papathomas ◽  
John M. Lauffer ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Electrical Characterization ◽  
Printed Wiring Board ◽  
Digital Products ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Wiring Board ◽  
Electronic Assemblies

Passives account for a very large part of today's electronic assemblies. This is particularly true for digital products such as cellular phones, camcorders, computers and several critical defense devices. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on organic multilayered substrates. A variety of thin film capacitor and resistors were utilized to manufacture high-performance embedded passives. The electrical properties of capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide temperature range. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. In both cases, capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Nanocomposite can be directly deposited either by liquid coating or screen printing. Alternatively, nanocomposite thin films can be laminated and capacitor laminate can be used as the base substrate for subsequent build-up processing. For example, Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. The capacitor fabrication is based on a sequential build-up technology employing a first patternable electrode. After patterning of the electrode, RC3 nanocomposite can be laminated within PCB. Embedded passive cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. Reliability of the capacitors was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1000 cycles DTC (Deep Thermal Cycle).

Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives

2010 ◽  
Vol 2010 (1) ◽  
pp. 000847-000854 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Steven G. Rosser ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
Thin Film ◽  
Flip Chip ◽  
Electrical Performance ◽  
Large Area ◽  
Capacitance Density ◽  
High Capacitance ◽  
Embedded Passives ◽  
Internal Core ◽  
Embedded Resistors ◽  
Carbon Based

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).

Effective Thermal Conductivity of Six Sigma’s Copper Reinforced Column Grid Array Interconnect for Ceramic Microelectronic Packages

2010 ◽  
Author(s):  
Mark Eblen
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Effective Thermal Conductivity ◽  
Flip Chip ◽  
Heat Removal ◽  
Thermal Design ◽  
Printed Wiring Board ◽  
Wiring Board ◽  
High Lead

Thermal management of flip chip style integrated circuits often relies on thermal conduction through the ceramic package and high lead solder grid array leads into the printed wiring board as the primary path for heat removal. Thermal analysis of this package configuration requires accurate characterization of the sometimes geometrically complex package-to-board interface. Given the unique structure of the Six Sigma column grid array (CGA) interconnect, a detailed finite element submodel was used to numerically derive the effective thermal conductivity with comparisons to a conventional CGA interconnect. Once an effective thermal conductivity value is obtained, the entire interconnect layer can be represented as a fictitious cuboid layer for inclusion in a more traditional “closed-form” thermal resistance calculation. This method allows the package designer a quick and robust method to evaluate initial thermal design study tradeoffs.

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000939-000957
Author(s):  
Florian Herrault ◽  
M. Yajima ◽  
M. Chen ◽  
C. McGuire ◽  
A. Margomenos
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Silicon Wafers ◽  
High Resistivity ◽  
3D Integration ◽  
Passive Components ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Lift Off ◽  
Rf Inductors

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.

Material and Electrical Characterization of HfO2 Films for MIM Capacitors Application

2003 ◽  
Vol 766 ◽  
Author(s):  
Hang Hu ◽  
Chunxiang Zhu ◽  
Y. F. Lu ◽  
Y. H. Wu ◽  
T. Liew ◽  
...  
Keyword(s):  
High Performance ◽  
Analog Circuit ◽  
Electrical Characterization ◽  
Capacitance Density ◽  
Force Microscopy ◽  
Low Leakage ◽  
Atomic Force ◽  
Low Leakage Current ◽  
Metal Insulator Metal ◽  
Mim Capacitors

AbstractThin films of HfO2 high-κ dielectric have been prepared by pulsed-laser deposition (PLD) at various deposition conditions. X-ray diffraction (XRD), atomic force microscopy (AFM), and secondary ion mass spectroscopy (SIMS) were used to characterize the deposited films. Experimental results show that substrate temperature has little effect on the stoichiometry, while deposition pressure plays an important role in determining the ratio of Hf and O. The electrical properties of HfO2 Metal-Insulator-Metal (MIM) capacitors were investigated at various deposition temperatures. It is shown that the HfO2 (56 nm) MIM capacitor fabricated at 200 oC shows an overall high performance, such as a high capacitance density of ∼3.0 fF/νm2, a low leakage current of 2x10-9 A/cm2 at 3 V, etc. All these indicate that the HfO2 MIM capacitors are very suitable for use in Si analog circuit applications.

The “Smeared” Property Technique for the FE Vibration Analysis of Printed Circuit Cards

1991 ◽  
Vol 113 (3) ◽  
pp. 250-257 ◽  
Author(s):  
J. M. Pitarresi ◽  
D. V. Caletka ◽  
R. Caldwell ◽  
D. E. Smith
Keyword(s):  
Natural Frequencies ◽  
Primary Objective ◽  
Mode Shapes ◽  
Fe Model ◽  
Printed Wiring Board ◽  
Modal Assurance Criterion ◽  
Printed Circuit ◽  
Wiring Board

The primary objective of this paper is to investigate the accuracy of the finite element (FE) smeared properties approach for the determination of the mode shapes and frequencies of a printed wiring board (PWB) populated with electronic modules. Smearing of the material and/or structural properties is a recognized means of reducing a complicated structure to a less complicated approximation. Comparisons of both the natural frequencies and mode shapes are made between the smeared FE model and those obtained from vibration testing. The extent of correlation between the mode shapes is characterized by the modal assurance criterion (MAC). Since the intent of this study is to examine the effectiveness of the smearing technique, free boundary conditions are assumed. It is shown that the smearing technique can produce good correlation of both natural frequencies and mode shapes of PWBs populated with modules. A case study of a PWB with both surface mount technology (SMT) and pin-in-hole (PIH) components is presented.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology

2012 ◽  
Vol 2012 (1) ◽  
pp. 000949-000954 ◽  
Author(s):  
Rabindra N. Das ◽  
John M. Lauffer ◽  
Frank D. Egitto ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Printed Wiring Board ◽  
Potential Cost ◽  
Multiple Substrates ◽  
Electrical Interconnection ◽  
Electrically Conductive Adhesive ◽  
Improved Performance ◽  
Novel Strategy ◽  
Wiring Board

Rigid-flex allows designers to replace multiple substrates interconnected with connectors, wires, and ribbon cables with a single package offering improved performance, reliability, and a potential cost-effective solution. However, processing and materials selection is critical in order to achieve high quality multilayer, rigid-flex structures. To date, there is no technology available which can economically produce high density multilayer rigid-flex with rigid or flex originating from any layer in the stack. In the present study, a novel strategy allowing for multi-layer rigid flex structures is reported. Specifically, metal-to-metal z-axis electrical interconnection among the flexible and rigid elements during lamination to form a single package rigid-flex structure is described. Conductive joints are formed during lamination using an electrically conductive adhesive (ECA). As a result, structures can be fabricated with multiple flexible elements at any arbitrary layer. Recent development work on flex joining using different pre-pregs is highlighted, particularly with respect to their integration in laminate chip carrier substrates, and the reliability of the joints formed between the rigid and flex surfaces. A variety of rigid-flex structures were fabricated, with 1 to 3 flex layers laminated into printed wiring board substrates. Photographs and optical microscopy were used to investigate the joining, bending, and failure mechanism. Several classes of flexible materials, including polyimides, PTFE, liquid crystal polymer (LCP), have been used to develop high-performance rigid-flex packages. Rigid-flex packages with embedded passives and actives are also being investigated.

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