Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000545-000566
Author(s):  
John Hunt ◽  
Adren Hsieh ◽  
Eddie Tsai ◽  
Chienfan Chen ◽  
Tsaiying Wang
Keyword(s):  
Temperature Cycling ◽  
Wafer Level ◽  
Development Activity ◽  
Wafer Level Packaging ◽  
First Case ◽  
Mask Design ◽  
To Come ◽  
And Performance ◽  
Reliability Performance ◽  
The Impact

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity. With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die. For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured. We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 000079-000085 ◽  
Author(s):  
Michael Toepper ◽  
Tanja Braun ◽  
Robert Gernhardt ◽  
Martin Wilke ◽  
Piotr Mackowiak ◽  
...  
Keyword(s):  
Laser Scanning ◽  
New Technology ◽  
Side Wall ◽  
Wafer Level ◽  
Major Barrier ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Low K ◽  
Metallization Process ◽  
Dry Film

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION

2012 ◽  
Vol 2012 (1) ◽  
pp. 000201-000208 ◽  
Author(s):  
Alberto Martins ◽  
Nelson Pinho ◽  
Harald Meixner
Keyword(s):  
Feedback Loop ◽  
High Volume ◽  
Data Availability ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Wafer Thickness ◽  
High Volume Production ◽  
Cte Mismatch ◽  
Volume Production ◽  
The Impact

NANIUM S.A. Portugal recently started producing eWLB fan-out [1][2] wafer level packaging technology on 300mm reconstituted wafers. Initial setup of this process demonstrated that the stable die Pick&Place accuracy plays a key role for product feasibility. In the subsequent volume production ramp-up it became apparent that the dynamic expansion of molded eWLB wafers, caused by thermal stress and CTE mismatch throughout the thin film redistribution and passivation layer up to bumping and reflow manufacturing processes requires a very tight die position monitoring over the complete wafer diameter. Feedback loop to the initial die placement and implementation of correction measures is essential to meet the quality and yield targets of different product configurations (die sizes, distance between dies, die thickness, wafer thickness, single die or system-inpackage) in high volume manufacturing. Stability and repeatability is of outermost importance. The paper will discuss the effects seen on the wafer, the monitoring and the strategies for feedback loop process enabling implementation of corrections into the reconstituted wafer before forming the artificial backend wafer by compression molding. The setup of adequate metrology steps throughout the process line supports the control of the various interlayer alignments. The end result is a centered process in the initial Pick&Place and various subsequent lithography steps (Stepper and Mask Aligner). Sustained data availability and processed data visualization made possible the development of an elaborate theoretical model enabling systematic optimizations of machine parameters and material expansion/compression correction factors. The model also permits the immediate visualization of the impact of each machine parameter on the global result.

Miniaturization of BAW devices and the impact of wafer level packaging technology

2013 ◽  
Author(s):  
Gernot Fattinger ◽  
Paul Stokes ◽  
Vishwavasu Potdar ◽  
Alexandre Volatier ◽  
Fabien Dumont ◽  
...  
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
The Impact

scholarly journals Internal Controls of the Municipality of Plaridel, Bulacan towards Good Governance

2021 ◽  
Vol 2 (6) ◽  
pp. 506-513
Author(s):  
Jerome Velasco
Keyword(s):  
Internal Control ◽  
Good Governance ◽  
Local Governance ◽  
Pearson Correlation ◽  
Vital Role ◽  
Policies And Procedures ◽  
Private And Public ◽  
To Come ◽  
And Performance ◽  
The Impact

Internal control plays a vital role in both private and public sectors. It is considered as one of the strategic tools in improving the operations and performance of an organization that will lead to the attainment of organizational goal and objectives. The main objective of the study was to determine the impact of control activities to the Municipality of Plaridel, Bulacan in complying with the good governance criteria. An assessment was conducted to determine the extent of control activities’ implementation in the organization to come up with the recommended measures for its further improvement. The study was based on a descriptive research design involving quantitative approach. Data gathered have been processed statistically using the SPSS by the Centro Escolar University Data Processing Center, and presented using the mean, standard deviation, and Pearson correlation analysis. The overall analysis revealed that the relationship between the extent of implementation and perceived impact of control activities to the Municipality in complying with the good governance criteria has a very significant relationship rating. Findings also showed that the existing implementation of control activities in the municipality can be further improved using the recommended measures focused on the following: Revisiting and Revising the existing policies and procedures, Strengthening the top Management’s functions, and Continuous professional development. It can be concluded that the implementation of control activities in the Municipality can improve the operations, and can contribute to the compliance with the Seal of Good Local Governance Criteria - financial administration aspect.

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000751-000773
Author(s):  
Craig Bishop ◽  
Suresh Jayaraman ◽  
Boyd Rogers ◽  
Chris Scanlan ◽  
Tim Olson
Keyword(s):  
New Technology ◽  
Minimum Size ◽  
High Yield ◽  
Wafer Level ◽  
Design Rules ◽  
Optical Scanner ◽  
Wafer Level Packaging ◽  
And Performance ◽  
The Cost ◽  
Semiconductor Chips

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Electromigration Characterization Versus Texture Analysis in Damascene Copper Interconnects

2000 ◽  
Vol 612 ◽  
Author(s):  
T. Berger ◽  
L. Arnaud ◽  
R. Gonella ◽  
I. Touet ◽  
G. Lormand
Keyword(s):  
Cross Sections ◽  
Ion Beam ◽  
Chemical Vapor ◽  
Grain Morphology ◽  
Diffusion Path ◽  
Wafer Level ◽  
Electroplated Copper ◽  
Reliability Performance ◽  
The Impact ◽  
Damascene Interconnects

AbstractWe have studied the effect of texture (X-ray diffraction pole figures) and grain morphology (Focus Ion Beam cross-sections) on the electromigration performances of copper damascene interconnects. Three different metallizations have been characterized : Chemical Vapor Deposition copper deposited on TiN (process A) and electroplated copper deposited either on Ta (process B) or TaN (process C). The reliability performance of these interconnects has been evaluated using both Wafer Level Reliability (WLR) and Package Level Reliability (PLR) tests on 4 and 0.6 νm wide lines using single metal level test structures. On the basis of the activation energy values and failure analysis observations, we concluded that interfacial diffusion plays a key role in the electromigration phenomenon for processes B and C whereas grain boundaries seem to be the active diffusion path for process A. The existence of several failure mechanisms during electromigration tests (interfacial or grain boundary diffusions), the impact of the damascene architecture on microstructure (sidewall textures and non columnar grain shapes) and the copper propensity for twinning seem to mask the impact of texture on the electromigration reliability of copper damascene interconnects.

scholarly journals Persistent Mobility Disability After Neurotoxic Chemotherapy

2010 ◽  
Vol 90 (11) ◽  
pp. 1649-1657 ◽  
Author(s):  
Elizabeth S. Hile ◽  
G. Kelley Fitzgerald ◽  
Stephanie A. Studenski
Keyword(s):  
Case Report ◽  
Peripheral Neuropathy ◽  
Older Adult ◽  
Functional Mobility ◽  
Cancer Treatments ◽  
Functional Deficits ◽  
First Case ◽  
Patient Reported ◽  
And Performance ◽  
The Impact

Background and Purpose The impact of cancer and its treatments on balance and functional mobility in older adults remains unknown but is increasingly important, given the evolution of cancer treatments. Subacute and more persistent side effects such as chemotherapy-induced peripheral neuropathy are on the rise, and the effects on mobility and balance, as well as the prognosis for resolution of any functional deficits, must be established before interventions can be trialed. The purpose of this case report is to describe the severity and long-term persistence of mobility decline in an older adult who received neurotoxic chemotherapy. To our knowledge, this is the first case report to describe an older adult with chemotherapy-induced peripheral neuropathy using results of standardized balance and mobility tests and to focus on prognosis by repeating these measures more than 2 years after chemotherapy. Case Description An 81-year-old woman received a neurotoxic agent (paclitaxel) after curative mastectomy for breast cancer. Baseline testing prior to taxane therapy revealed a socially active woman with no reported functional deficits or neuropathic symptoms, 1.2-m/s gait speed, and performance at the ceiling on balance and gait portions of a standardized mobility measure. Outcomes After 3 cycles, paclitaxel therapy was stopped by the oncologist because of neurotoxicity. Declines as large as 50% were seen in performance-based measures at 12 weeks and persisted at 2.5 years, and the patient reported recurrent falls, cane use, and mobility-related disability. Discussion This case highlights the extent to which function can decline in an older individual receiving neurotoxic chemotherapy, the potential for these deficits to persist years after treatment is stopped, and the need for physical therapy intervention and further research in this population.

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