Optimization of Lead Free Plating for Flip Chip Applications

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001553-001602
Author(s):  
Charles L. Arvin ◽  
Jurg Stahl ◽  
Wolfgang Sauter ◽  
Harry cox ◽  
Eric Perfecto ◽  
...  
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Assembly Process ◽  
Solder Bumps ◽  
Free Solder ◽  
The Right ◽  
Pure Cu ◽  
Final Composition ◽  
Solder Composition ◽  
Sac Solder

Traditional flip chip processes have consolidated to a SnAgCu (SAC) solder system. Each company based upon their own needs and application space has come to their own method to achieve the desired final composition of the interconnect. These have included different solder compositions for both the pre-solder and the C4. The various interconnect solutions can range from no solder on one side such as pure Cu or Ni to an interconnect that has identical solder composition for both the substrate and the C4. Decisions for the optimized solution include the need for reliability, cost and yield. Picking the right solution also enables the elimination of defects such as solder voids, interfacial voids, white bumps, micro-solder bumps and non-wets. The optimized solutions are dependent upon many factors that include the fragility of the silicon dielectric, the size of the die, type of flux used at assembly, the assembly process used, method by which SnAg is plated such as various layering techniques, final processes steps in C4, test probe concepts, DSP methods and many more. In order to pick the appropriate scheme for each product and for each industry, it is imperative to know the interaction of all of these factors. This paper provides concepts and data about how to optimize assembly and lead free plating for a particular process. In the plating process, this includes the importance of various layering steps and analysis of incoming chemicals, especially the acids, and in the assembly process, the knowledge and matching of solder hierarchy, warpage, flux characteristics and preparation / cleaning steps prior to underfill. In particular, we will provide the data and the scheme by which it is possible to produce void free solder processes without bleed and feed on SnAg baths that are over 100 amp-hr per liter and over 1 year old.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

2002 ◽  
Vol 12 (10) ◽  
pp. 372-374 ◽  
Author(s):  
K. Onodera ◽  
T. Ishii ◽  
S. Aoyama ◽  
S. Sugitani ◽  
M. Tokumitsu
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Flip Chip Bonding ◽  
W Band ◽  
Solder Bumps ◽  
Bonding Technology ◽  
Free Solder

Microstructure Comparison of Soldered Joints Using Electrochemical Selective Etching

2012 ◽  
Vol 729 ◽  
pp. 367-372 ◽  
Author(s):  
Tamás Hurtony ◽  
Attila Bonyár ◽  
Péter Gordon
Keyword(s):  
Cross Section ◽  
Electrochemical Etching ◽  
Lead Free ◽  
Lead Free Solder ◽  
Cross Sectional ◽  
Reflow Soldering ◽  
Solder Bumps ◽  
Lead Free Solder Alloy ◽  
Free Solder ◽  
Sac Solder

The microstructure of the commonly used SnAgCu (SAC) lead free solder alloy was investigated. SAC solder bumps were soldered by two different soldering techniques (Vapor Phase Soldering (VPS), Laser reflow). Since the soldering profile of the VPS method is considerably different from the temperature profile of the laser reflow soldering, the created microstructures are expected to be diverse. Selective electrochemical etching was applied on cross sectional samples in order to extract the tin from the cross sectioning plane. In this manner the spatial structure of Cu6Sn5and the Ag3Sn intermetllic compounds (IMCs) was highlighted. The microstructures of the samples were analyzed with optical microscopy and Scanning Electron Microscope (SEM) on cross-section samples. The composing elements were identified by SEM-EDS.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

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