Microfabrication and Packaging Process for a Single-Chip Position, Navigation, and Timing System

2017 ◽  
Vol 2017 (1) ◽  
pp. 000208-000214 ◽  
Author(s):  
Junjun Huan ◽  
Vamsy P. Chodavarapu ◽  
George Xereas ◽  
Charles Allan
Keyword(s):  
Inertial Sensors ◽  
Low Cost ◽  
Autonomous Systems ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
High Volume ◽  
Leak Rate ◽  
Single Chip ◽  
Wafer Level ◽  
Crystal Silicon

Abstract The Global Positioning System (GPS) is the primary means of Positioning, Navigation, and Timing (PNT) for most civilian and military systems and applications. The rapid growth in autonomous systems has created a widespread interest in self-contained Inertial Navigation System (INS) for precise navigation and guidance in the absence of GPS. The microscale PNT systems need both specialized and low cost fabrication technologies to cost effectively bring these technologies to market. We describe an ultra-clean (low leak rate) wafer-level vacuum encapsulation microfabrication process of Micro-Electro-Mechanical Systems (MEMS) based sensors and devices. Using this process we have fabricated inertial sensors, frequency reference resonators, and pressure sensors. In addition to providing excellent resistance to shock and vibration, this combined microfabrication and packaging method would allow the use of high volume low cost plastic packaging at the device level. The microfabrication process is an 8” wafer process based on high aspect ratio bulk micromachining of a 30 μm thick single-crystal silicon device layer that is vacuum encapsulated at 10 mTorr between two silicon wafers with the demonstrated leak rate of only 6.5 × 10−18 atm cm3/s.

Assembly and Testing of Surface Micromachined, Piezoresistive Polysilicon Pressure Sensors

1999 ◽  
Author(s):  
Todd F. Miller ◽  
David J. Monk ◽  
Gary O’Brien ◽  
William P. Eaton ◽  
James H. Smith
Keyword(s):  
Pressure Sensor ◽  
Microelectromechanical Systems ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
Surface Micromachining ◽  
Process Technology ◽  
Crystal Silicon ◽  
Noise Characteristics ◽  
Testing Techniques ◽  
Piezoresistive Pressure Sensors

Abstract Surface micromachining is becoming increasingly popular for microelectromechanical systems (MEMS) and a new application for this process technology is pressure sensors. Uncompensated surface micromachined piezoresistive pressure sensors were fabricated by Sandia National Labs (SNL). Motorola packaged and tested the sensors over pressure, temperature and in a typical circuit application for noise characteristics. A brief overview of surface micromachining related to pressure sensors is described in the report along with the packaging and testing techniques used. The electrical data found is presented in a comparative manner between the surface micromachined SNL piezoresistive polysilicon pressure sensor and a bulk micromachined Motorola piezoresistive single crystal silicon pressure sensor.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

Micro-Patterning of Silicon by Frictional Interaction and Chemical Reaction

1998 ◽  
Vol 120 (2) ◽  
pp. 353-357 ◽  
Author(s):  
Dae-Eun Kim ◽  
Jae-Joon Yi
Keyword(s):  
Chemical Reaction ◽  
Low Cost ◽  
Three Dimensional ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Micro Electro Mechanical Systems ◽  
Micro Patterning ◽  
Frictional Interaction ◽  
Micro Structures ◽  
Micro Patterns

In this paper a novel and economical method of generating three-dimensional micro-patterns on single crystal silicon without the need for a mask is presented. The technique is based on the fundamental understanding of frictional interaction at light loads. Micro-patterning is done through a two-step process that comprises mechanical scribing and chemical etching. The basic idea is to induce micro-plastic deformation along a prescribed track through frictional interaction between the tool and the workpiece. Then, by exposing the surface to a chemical under controlled conditions, preferential chemical reaction is induced along the track to form hillocks about 5 μm wide and 1 μm high. This method of micro-machining may be used for making patterns in micro-electro-mechanical systems (MEMS) at low cost. Furthermore, this process demonstrates how microtribological processes can be utilized in the fabrication of micro-structures.

Design and Optimization of a Highly Sensitive and Linearity Piezoresistive Pressure Sensor Based on a Combination of Cross Beam-Peninsula-Membrane Structure

2017 ◽  
Author(s):  
Tran Anh Vang ◽  
Xianmin Zhang ◽  
Benliang Zhu
Keyword(s):  
Pressure Sensor ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
High Sensitivity ◽  
Crystal Silicon ◽  
Nonlinearity Error ◽  
Trade Off ◽  
Design And Optimization ◽  
Piezoresistive Pressure Sensor ◽  
Piezoresistive Pressure Sensors

The sensitivity and linearity trade-off problem has become the hotly important issues in designing the piezoresistive pressure sensors. To solve these trade-off problems, this paper presents the design, optimization, fabrication, and experiment of a novel piezoresistive pressure sensor for micro pressure measurement based on a combined cross beam - membrane and peninsula (CBMP) structure diaphragm. Through using finite element method (FEM), the proposed sensor performances as well as comparisons with other sensor structures are simulated and analyzed. Compared with the cross beam-membrane (CBM) structure, the sensitivity of CBMP structure sensor is increased about 38.7 % and nonlinearity error is reduced nearly 8%. In comparison with the peninsula structure, the maximum non-linearity error of CBMP sensor is decreased about 40% and the maximum deflection is extremely reduced 73%. Besides, the proposed sensor fabrication is performed on the n-type single crystal silicon wafer. The experimental results of the fabricated sensor with CBMP membrane has a high sensitivity of 23.4 mV/kPa and a low non-linearity of −0.53% FSS in the pressure range 0–10 kPa at the room temperature. According to the excellent performance, the sensor can be applied to measure micro-pressure lower than 10 kPa.

Microsensors for Automotive Applications – Metrology and Test

2001 ◽  
Vol 687 ◽  
Author(s):  
Gottfried Flik ◽  
Heinz Eisenschmid ◽  
Carsten Raudzis ◽  
Frank Schatz ◽  
Winfried Schoenenborn ◽  
...  
Keyword(s):  
Inertial Sensors ◽  
Pressure Sensors ◽  
Critical Parameters ◽  
Design For Test ◽  
Sensor Design ◽  
Wafer Level ◽  
Process Technology ◽  
Test Procedures ◽  
Silicon Bulk ◽  
Critical Model

AbstractAccording to market surveys automotive microsensors will evolve into a multi-billion dollar business by 2005. Key roles are attributed to inertial sensors for passenger safety systems, and mass flow and pressure sensors for engine management systems. Thin film techniques together with silicon bulk or surface micromachining have been established as preferential processes to achieve reduction of sensor size, weight and cost along with improvements of sensor functionality and reliability. Enhanced sensor performance often pushes the limits of process technology and therefore the need arises very early in the MEMS design process to identify materials and geometry related parameters which are critical with respect to their tolerance band specifications. In order to control these critical parameters, automated wafer level test procedures need to be developed (based preferentially on electrical quantities) and additionally considered for in the sensor design phase (design for test). In analogy to microelectronics 2D wafer maps of critical parameters may give hints on how to improve process stability and how to adapt the sensor design in order to optimize yield. Examples of critical model parameter variations include thermal conductivity, thickness, and shear modulus of thin films.

Semi-automatic, volume production of silicon solar cells

1987 ◽  
Vol 65 (8) ◽  
pp. 892-896 ◽  
Author(s):  
R. E. Thomas ◽  
C. E. Norman ◽  
S. Varma ◽  
G. Schwartz ◽  
E. M. Absi
Keyword(s):  
Solar Cells ◽  
Single Crystal ◽  
Plasma Etching ◽  
Low Cost ◽  
Single Crystal Silicon ◽  
High Yield ◽  
Silicon Solar Cells ◽  
Crystal Silicon ◽  
Volume Production ◽  
P Type

A low-cost, high-yield technology for producing single-crystal silicon solar cells at high volumes, and suitable for export to developing countries, is described. The process begins with 100 mm diameter as-sawn single-crystal p-type wafers with one primary flat. Processing steps include etching and surface texturization, gaseous-source diffusion, plasma etching, and contacting via screen printing. The necessary adaptations of such standard processes as diffusion and plasma etching to solar-cell production are detailed. New process developments include a high-throughput surface-texturization technique, and automatic printing and firing of cell contacts.The technology, coupled with automated equipment developed specifically for the purpose, results in solar cells with an average efficiency greater than 12%, a yield exceeding 95%, a tight statistical spread on parameters, and a wide tolerance to starting substrates (including the first 100 mm diameter wafers made in Canada). It is shown that with minor modifications, the present single shift 500 kWp (kilowatt peak) per year capacity technology can be readily expanded to 1 MWp per year, adapted to square and polycrystalline substrates, and efficiencies increased above 13%.

scholarly journals Review on Pressure Sensors: A Perspective from Mechanical to Micro-electro-mechanical systems

2021 ◽  
Author(s):  
Ankur Gupta
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Pressure Sensors ◽  
Micro Electro Mechanical System ◽  
Single Chip ◽  
Micro Electro Mechanical Systems ◽  
Compact Size ◽  
Wide Range ◽  
Fabrication Procedure ◽  
Application Requirements

Swiftly emerging research prospects in the Micro-Electro-Mechanical System (MEMS) enable to build of complex and sophisticated microstructures on a substrate containing moving masses, cantilevers, flexures, levers, linkages, dampers, gears, detectors, actuators, and many more on a single chip. One of the MEMS initial products that emerged into the micro-system technology is the MEMS pressure sensor. Because of their high performance, low cost, and compact size, these sensors are extensively being adopted in numerous applications viz., aerospace, automobile, and bio-medical domain, etc. These application requirements drive and impose tremendous conditions on sensor design to overcome the tedious design and fabrication procedure before its reality. MEMS-based pressure sensors enable a wide range of pressure measurements as per the application requirements. Considering its vast utility in industries, this paper presents a detailed review of MEMS-based pressure sensors and their wide area of applications, their design aspects, and challenges, to provide state of an art gist to the researchers of a similar domain in one place.

CuInSe2 Thin Film Modules for Utility Applications

1994 ◽  
Vol 116 (1) ◽  
pp. 25-27
Author(s):  
C. Fredric ◽  
D. Tarrant ◽  
C. Jensen ◽  
J. Hummel ◽  
J. Ermer
Keyword(s):  
Thin Film ◽  
Large Scale ◽  
Low Cost ◽  
Single Crystal Silicon ◽  
Outdoor Exposure ◽  
Production Costs ◽  
Scale Production ◽  
Large Area ◽  
Crystal Silicon ◽  
Thin Film Fabrication

Recent advances in the efficiency and manufacturing technology of CuInSe2 (CIS) thin films demonstrate the opportunity for low-cost large-scale production of photovoltaics for utility applications. Large area (0.4 m2) submodules with 9.7 percent aperture efficiencies yielding 37.8 watts have been fabricated. Thin film fabrication techniques used in the production of modules enable reduced production costs compared with those for single crystal silicon. The performance of 0.4 m2 modules is projected to exceed 50 watts, based on performance achieved to date on 0.1 m2 modules and small area test devices. Preliminary tests packaged (encapsulated and framed) modules show no significant losses after 15 1/2 months of continuous outdoor exposure. Fabrication of 0.4 m2 modules to demonstrate the feasibility of large-scale commercialization of CIS thin film photovoltaics for utility applications is currently under way.

Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

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