High performance no-flow underfills for low-cost flip-chip applications: material characterization

1998 ◽  
Vol 21 (3) ◽  
pp. 450-458 ◽  
Author(s):  
C.P. Wong ◽  
S.H. Shi ◽  
G. Jefferson
Keyword(s):  
Material Characterization ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000611-000638
Author(s):  
Jonathan Prange ◽  
Yi Qin ◽  
Matthew Thorseth ◽  
Inho Lee ◽  
Masaaki Imanari ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Lead Free ◽  
Lead Free Solder ◽  
Next Generation ◽  
Copper Nickel ◽  
Microelectronic Devices ◽  
Architectural Features ◽  
Free Solder

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Correlation Between the Mechanical Strength and Curing Condition of No-Flow Flip Chip Assemblies

2002 ◽  
Vol 124 (4) ◽  
pp. 397-402 ◽  
Author(s):  
C. W. Tang ◽  
Y. C. Chan ◽  
K. C. Hung ◽  
P. L. Tu
Keyword(s):  
Mechanical Strength ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Under Bump Metallization ◽  
Assembly Technique ◽  
Curing Condition ◽  
Flip Chip Assembly ◽  
Relationship Of ◽  
Interconnect Technology

Flip chip is the emerging interconnect technology for the next generation of high performance electronics. To eliminate the process bottlenecks associated with flip chip assembly, a new assembly technique based around “No-flow” underfill formulations has been proposed. In this paper, we have studied the correlation between the mechanical strength and the curing condition of no-flow flip chip assemblies using six different reflow profiles. It is found that both Ni3Sn4 and Cu6Sn5 intermetallics (IMCs) are formed at the solder/substrate pad and UBM (Under Bump Metallization)/solder interfaces respectively. The thickness of both IMCs increase with the increasing heating factor. The characteristics of the mechanical strength of these IMCs have been demonstrated. A correlation between the mechanical strength and the interfacial metallurgical reaction has been discussed. Also, the fastest possible reflow profile for both the cure of the underfill and maximizing the shear strength is identified. Based on the observed relationship of the mechanical strength and underfill curing of no-flow flip chip assemblies with Qn, the reflow profile should be controlled with caution in order to optimize both the mechanical strength and time for underfill cure. Only a clearer understanding of these correlation can allow manufacturers to develop a optimal, high reliable, low cost, high throughput no-flow flip chip assembly process.

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-41 ◽  
Author(s):  
Lewis(In Soo) Kang
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Industrial Applications ◽  
System Control ◽  
Wafer Level ◽  
Communication Module ◽  
3D Packaging ◽  
Control Application ◽  
Wafer Level Package

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

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