The Effect of Nickel Oxidation Formed in the Interface of ENEPIG Structure for Flip Chip Technology

Abstract In flip chip assembly, the smaller solder ball is used in chip and substrate joint. This may have an adverse influence on the reliability of electronic products. Thus, the mechanical strength of solder joint is an important topic for the major reliability in electronic assembly technology. We found the intermetallic compound (IMC) crack issue for Electroless Ni(P) / Electroless Pd(P) / Immersion Au (ENEPIG) Interposer product. In this study, we analyzed the failure samples, for ENEPIG processes verified to find out the IMC crack root cause. The interposer pad structure for these samples was manufactured by ENEPIG process, in which the formation of the oxidation layer is affected by the duration that the sample is exposed on top of Ni bath. These samples print solder paste were performed multi-times reflow for ENEPIG and solder interfacial reaction observation to clarify the nickel oxidation influence on crack issue. These samples were observed and analyzed by Scanning Electron Microscope (SEM), Focused Ion Beam (FIB), Transmission Electron Microscope (TEM), and Energy-Dispersive X-ray Spectroscopy (EDX). The interface strength between ENEPIG and solder were tested by hot bump pull test (HBP), and also has the adhesion analysis. The results show that with the shorter exposure on top of nickel bath is no nickel oxidation formed and the interface has a higher pull strength, with a longer exposure on top of nickel bath had more nickel oxidation formed in the ENEPIG interface and also reveal lower pull strength. Therefore, the IMC crack was induced by the void at ENEPIG interface, which was the reaction of nickel oxidation and Au chemical, and the control of the exposure time on top of nickel bath can inhibit the oxidation formation to reduce the IMC crack risk.

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Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2009p0081 ◽

2009 ◽

Author(s):

E. Hendarto ◽

S.L. Toh ◽

J. Sudijono ◽

P.K. Tan ◽

H. Tan ◽

...

Keyword(s):

Electron Microscope ◽

Focused Ion Beam ◽

Failure Modes ◽

Ion Beam ◽

Electrical Characterization ◽

Nickel Silicide ◽

Fault Isolation ◽

Technology Nodes ◽

Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

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Focused Ion Beam Analysis of Low-K Dielectrics

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0397 ◽

2000 ◽

Author(s):

H. J. Bender ◽

R. A. Donaton

Keyword(s):

Electron Microscope ◽

Cross Section ◽

Focused Ion Beam ◽

Ion Beam ◽

Single Step ◽

Specimen Preparation ◽

Transmission Electron ◽

Beam Analysis ◽

Low K ◽

Scanning Electron

Abstract The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.

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FIB Enhancement of Mechanically Polished Cross-sections

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0232 ◽

2019 ◽

Author(s):

Becky Holdford

Keyword(s):

Electron Microscope ◽

High Resolution ◽

Scanning Electron Microscope ◽

Cross Sections ◽

Focused Ion Beam ◽

Ion Beam ◽

High Resolution Imaging ◽

Chemical Attack ◽

Resolution Imaging ◽

Scanning Electron

Abstract On mechanically polished cross-sections, getting a surface adequate for high-resolution imaging is sometimes beyond the analyst’s ability, due to material smearing, chipping, polishing media chemical attack, etc.. A method has been developed to enable the focused ion beam (FIB) to re-face the section block and achieve a surface that can be imaged at high resolution in the scanning electron microscope (SEM).

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Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0229 ◽

2016 ◽

Author(s):

Julien Goxe ◽

Béatrice Vanhuffel ◽

Marie Castignolles ◽

Thomas Zirilli

Keyword(s):

Electron Microscope ◽

Scanning Electron Microscope ◽

Sample Preparation ◽

Failure Analysis ◽

Focused Ion Beam ◽

Ion Beam ◽

Silicon On Insulator ◽

Mixed Signal ◽

Voltage Contrast ◽

Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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Metallic Nanoneedles Arrays for TEM Sample Preparation “Lift-Out”

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0379 ◽

2012 ◽

Author(s):

Romaneh Jalilian ◽

David Mudd ◽

Neil Torrez ◽

Jose Rivera ◽

Mehdi M. Yazdanpanah ◽

...

Keyword(s):

Mechanical Properties ◽

Electron Microscope ◽

Sample Preparation ◽

Focused Ion Beam ◽

Ion Beam ◽

Beam System ◽

Transmission Electron ◽

Nanoneedle Array ◽

Superior Mechanical Properties ◽

And Performance

Abstract The sample preparation for transmission electron microscope can be done using a method known as "lift-out". This paper demonstrates a method of using a silver-gallium nanoneedle array for a quicker sharpening process of tungsten probes with better sample viewing, covering the fabrication steps and performance of needle-tipped probes for lift-out process. First, an array of high aspect ratio silver-gallium nanoneedles was fabricated and coated to improve their conductivity and strength. Then, the nanoneedles were welded to a regular tungsten probe in the focused ion beam system at the desired angle, and used as a sharp probe for lift-out. The paper demonstrates the superior mechanical properties of crystalline silver-gallium metallic nanoneedles. Finally, a weldless lift-out process is described whereby a nano-fork gripper was fabricated by attaching two nanoneedles to a tungsten probe.

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Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0128 ◽

2008 ◽

Author(s):

Steven B. Herschbein ◽

Hyoung H. Kang ◽

Scott L. Jansen ◽

Andrew S. Dalton

Keyword(s):

Flip Chip ◽

Focused Ion Beam ◽

Ion Beam ◽

Random Access ◽

Cell Counting ◽

Test Results ◽

Laboratory Procedure ◽

Memory Array ◽

Dual Beam ◽

Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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