Packaging Renaissance with Chiplets

Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.

Download Full-text

Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000088 ◽

2021 ◽

pp. 1-9

Author(s):

Philipp Ritter

Keyword(s):

Millimeter Wave ◽

Flip Chip ◽

Printed Circuit Board ◽

Digital Signal ◽

Cmos Technology ◽

Radar System ◽

Circuit Board ◽

Processing Unit ◽

Automotive Radar ◽

On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Download Full-text

Research and Introduction of the Process Flow of Full-automatic Wafer Level Flip Chip Machine

2018 19th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2018.8480617 ◽

2018 ◽

Author(s):

He Yunbo ◽

Gao Jian ◽

Chen Yun ◽

Ye Wentao ◽

Chen Xun ◽

...

Keyword(s):

Flip Chip ◽

Wafer Level ◽

Process Flow

Download Full-text

Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects

Proceedings of the 2007 international workshop on System level interconnect prediction - SLIP '07 ◽

10.1145/1231956.1231973 ◽

2007 ◽

Cited By ~ 6

Author(s):

Hoyeol Cho ◽

Kyung-Hoae Koo ◽

Pawan Kapur ◽

Krishna C. Saraswat

Keyword(s):

Carbon Nanotube ◽

Global Interconnects ◽

On Chip ◽

Nanotube Bundle ◽

Low K

Download Full-text

Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates

2012 IEEE 62nd Electronic Components and Technology Conference ◽

10.1109/ectc.2012.6248992 ◽

2012 ◽

Cited By ~ 7

Author(s):

Jae-Woong Nah ◽

Michael Gaynes ◽

Eric Perfecto ◽

Claudius Feger

Keyword(s):

Flip Chip ◽

Organic Substrates ◽

Wafer Level ◽

Cu Pillar ◽

Area Array ◽

Flip Chip Packaging ◽

Low K

Download Full-text

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1 ◽

10.1115/ipack2011-52078 ◽

2011 ◽

Author(s):

Pushkraj Tumne ◽

Vikram Venkatadri ◽

Santosh Kudtarkar ◽

Michael Delaus ◽

Daryl Santos ◽

...

Keyword(s):

Flip Chip ◽

Bulk Solder ◽

Consumer Electronics ◽

Drop Test ◽

Design Parameters ◽

Mechanical Shock ◽

Wafer Level ◽

Cross Sectional ◽

Right Censored Data ◽

Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Download Full-text

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

10.1115/imece2000-2248 ◽

2000 ◽

Author(s):

Y. T. Lin ◽

P. J. Tang ◽

K. N. Chiang

Keyword(s):

Reliability Analysis ◽

Flip Chip ◽

Parametric Design ◽

Material Selection ◽

New Technology ◽

Rapid Expansion ◽

Wafer Level ◽

Good Reliability ◽

Wafer Level Packaging ◽

Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Download Full-text

A test of prospect theory

International Journal of Technology Assessment in Health Care ◽

10.1017/s0266462305050713 ◽

2005 ◽

Vol 21 (4) ◽

pp. 511-516 ◽

Cited By ~ 5

Author(s):

David Feeny ◽

Ken Eng

Keyword(s):

Total Hip Arthroplasty ◽

Prospect Theory ◽

Reference Point ◽

Standard Gamble ◽

Health States ◽

Current Health ◽

Current State ◽

Direction Opposite ◽

Better Than ◽

Utility Scores

Objectives: Prospect theory (PT) hypothesizes that people judge states relative to a reference point, usually assumed to be their current health. States better than the reference point are valued on a concave portion of the utility function; worse states are valued on a convex portion. Using prospectively collected utility scores, the objective is to test empirically implications of PT.Methods: Osteoarthritis (OA) patients undergoing total hip arthroplasty periodically provided standard gamble scores for three OA hypothetical states describing mild, moderate, and severe OA as well as their subjectively defined current state (SDCS). Our hypothesis was that most patients improved between the pre- and postsurgery assessments. According to PT, scores for hypothetical states previously > SDCS but now < SDCS should be lower at the postsurgery assessment.Results: Fourteen patients met the criteria for testing the hypothesis. Predictions were confirmed for 0 patients; there was no change or mixed results for 6 patients (42.9 percent); and scores moved in the direction opposite to that predicted by PT for 8 patients (57.1 percent).Conclusions: In general, the direction and magnitude of the changes in hypothetical-state scores do not conform to the predictions of PT.

Download Full-text