The Microelectronic Wire Bond: Past, Present, and Future

2010 ◽  
Vol 2010 (1) ◽  
pp. 000462-000469
Author(s):  
Harry K. Charles

Since its very inception, the microelectronic wire bond has been the dominate form of first-level interconnection (chip to package or substrate). Wire bonds account for over 80% of first-level chip interconnections made by the microelectronic industry each year. Wire bonding is reliable, flexible, and low cost when compared to other forms of first-level interconnections. In this article a brief discussion of wire bonding is presented along with bond formation fundamentals. Aspects of wire bond reliability will be explored in conjunction with methods of wire bond testing. Particular attention is given to fine pitch bonding, bonding to stacked die, higher frequency bonding, ball bonding with copper wire, and advanced bond testing methods.

2015 ◽  
Vol 2015 (1) ◽  
pp. 000406-000412 ◽  
Author(s):  
Ivy Qin ◽  
Aashish Shah ◽  
Hui Xu ◽  
Bob Chylak ◽  
Nelson Wong

With all the advances in 2.5D and 3D packaging, wire bonding is still the most popular interconnect technology and the workhorse of the industry. Wire bonding technology has been the lower cost solution comparing to flip chip. Wire bonding package cost is much reduced with the introduction of Copper wire bonding. Technology development and innovation in wire bonding provides new packaging solutions that improves performance and reduces cost. This paper reviews the recent innovations in ball bonding technology to provide optimized ball bonding solutions targeted for different bonding wire material. It examines the different challenges for the alternative wire types including Cu wire, Pd coated, and AuPd coated Cu wire and Ag Alloy wire. We will discuss key development in ball bonding equipment, process and material to overcome the challenges and provide robust low cost solutions. The advantages of each wire type are outlined, and guidelines to select the right bonding wire type per application requirements are provided.


Author(s):  
Subramani Manoharan ◽  
Chandradip Patel ◽  
Patrick McCluskey

Silver is a leading competitor to gold and copper in fine pitch wire bonding used in the interconnection of microelectronic devices. Primary material for wire bonding has been gold, which gave way to copper in order for original equipment manufacturers to realize cost benefits. However, copper wire bonding has exhibited several reliability issues, especially in industrial and high temperature applications. Corrosion is the major problem, which was mitigated by coating the wire with palladium, which increased overall cost of production. Other concerns include harder free air ball (FAB) leading to under pad metallization cracking, smaller process window, excessive aluminum splash especially in fine pitch bonding, and lower throughput and yield arising from the hardness and stiffness of copper. Due to the above concerns, automotive, military and aerospace industries are still reluctant to fully adopt copper wire bonding. Light emitting diodes (LEDs) are also not manufactured with copper wires due to its low reflectance. Some of these industries are still using gold wire bonds in most of their packages, but are continually looking for an alternative. Silver wire bonds have good electrical and thermal conductivity, are less prone to corrosion than copper, have low melting points and comparable hardness to gold. Also, cost of silver has been shown to be similar to that of palladium coated copper wire, hence making it a good alternative. Silver wire bonding, a relatively new area of research, has attracted a lot of research focused on wire dopant material, bonding process, quality and reliability. This paper is aimed to serve as a comprehensive review of research done in this area, by summarizing the literature on silver wire bonding, establishing benefits and drawbacks over other wire bond materials and indicating reliability concerns along with failure modes and mechanisms.


Author(s):  
Huixian Wu ◽  
Arthur Chiang ◽  
David Le ◽  
Win Pratchayakun

Abstract With gold prices steadily going up in recent years, copper wire has gained popularity as a means to reduce cost of manufacturing microelectronic components. Performance tradeoff aside, there is an urgent need to thoroughly study the new technology to allay any fear of reliability compromise. Evaluation and optimization of copper wire bonding process is critical. In this paper, novel failure analysis and analytical techniques are applied to the evaluation of copper wire bonding process. Several FA/analytical techniques and FA procedures will be discussed in detail, including novel laser/chemical/plasma decapsulation, FIB, wet chemical etching, reactive ion etching (RIE), cross-section, CSAM, SEM, EDS, and a combination of these techniques. Two case studies will be given to demonstrate the use of these techniques in copper wire bonded devices.


Author(s):  
Pradeep Lall ◽  
Sungmo Jung

Abstract Electronics in automotive underhood environments may be subjected to high temperature in the range of 125–200°C. Transition to electric vehicles has resulted in need for electronics capable of operation under high voltage bias. Automotive electronics has simultaneously transitioned to copper wire-bond from gold wire-bond for first-level interconnections. Copper has a smaller process window and a higher propensity for corrosion in comparison with gold wire bonds. There is scarce information on the reliability of copper wire bonds in presence of high voltage bias under operation at high temperature. In this paper, a multiphysics model for micro galvanic corrosion in the presence of chlorine is introduced. The diffusion cell is used to measure the diffusivity of chlorine in different pH values and different temperatures. Diffusivity measurements are incorporated into the 3D ionic transport model to study the effect of different environmental factors on the transport rate of chlorine. The tafel parameters for copper, aluminum and intermetallics have been extracted through measurements of the polarization curves. The multiple physics of ionic transport in presence of concentration gradient, potential gradient is coupled with the galvanic corrosion.


2014 ◽  
Vol 609-610 ◽  
pp. 1153-1158
Author(s):  
Dong Rui Wang ◽  
Mei Liu

The wire bonding process in the package of MEMS accelerometer is analyzed by the finite element software ANSYS/LS-DYNA. Impact on the bonding strength of the ultrasonic amplitude, ultrasonic frequency and the friction between wire bond and bond pad are studied. The strength of wire bond is evaluated through the bond pull test experiment. The test result shows that the analysis on the wire bonding is helpful for improving the quality of wire bonding.


Author(s):  
Pradeep Lall ◽  
Shantanu Deshpande ◽  
Luu Nguyen

Gold wire bonding has been widely used as first-level interconnect in semiconductor packaging. The increase in the gold price has motivated the industry search for alternative to the gold wire used in wire bonding and the transition to copper wire bonding technology. Potential advantages of transition to Cu-Al wire bond system includes low cost of copper wire, lower thermal resistivity, lower electrical resistivity, higher deformation strength, damage during ultrasonic squeeze, and stability compared to gold wire. However, the transition to the copper wire brings along some trade-offs including poor corrosion resistance, narrow process window, higher hardness, and potential for cratering. Formation of excessive Cu-Al intermetallics may increase electrical resistance and reduce the mechanical bonding strength. Current state-of-art for studying the Cu-Al system focuses on accumulation of statistically significant number of failures under accelerated testing. In this paper, a new approach has been developed to identify the occurrence of impending apparently-random defect fall-outs and pre-mature failures observed in the Cu-Al wirebond system. The use of intermetallic thickness, composition and corrosion as a leading indicator of failure for assessment of remaining useful life for Cu-al wirebond interconnects has been studied under exposure to high temperature and temperature-humidity. Damage in wire bonds has been studied using x-ray Micro-CT. Microstructure evolution was studied under isothermal aging conditions of 150°C, 175°C, and 200°C till failure. Activation energy was calculated using growth rate of intermetallic at different temperatures. Effect of temperature and humidity on Cu-Al wirebond system was studied using Parr Bomb technique at different elevated temperature and humidity conditions (110°C/ 100%RH, 120°C/ 100%RH, 130°C/ 100%RH) and failure mechanism was developed. The present methodology uses evolution of the IMC thickness, composition in conjunction with the Levenberg-Marquardt algorithm to identify accrued damage in wire bond subjected to thermal aging. The proposed method can be used for quick assessment of Cu-Al parts to ensure manufactured part consistency through sampling.


Author(s):  
Leong Ching Wai ◽  
Norhanani Binte Jaafar ◽  
Michelle Chew ◽  
Sivakumar ◽  
Gunasekaran ◽  
...  

2018 ◽  
Vol 2018 (1) ◽  
pp. 000583-000588 ◽  
Author(s):  
Hui Xu ◽  
Aashish Shah ◽  
Basil Milton ◽  
Ivy Qin

Abstract Wire bonding continues to be the most commonly used interconnection technology due to its low cost, high yield rate, increased flexibility and improved reliability. Among wire bonded packages, the high growth areas include Multi-Chip modules and System in Package (SiP) applications. A type of wire bonding, Stand-Off-Stitch Bond (SSB), is widely used in Multi-chip, die-to-die, SiP and light-emitting diodes (LEDs). The SSB process starts with a flat-topped bump bonding on the substrate or die, followed by the formation of a new ball bond (1st bond). The stitch bond (2nd bond) of that wire is bonded on top of the initial bump. This paper focuses on key SSB process steps, by examining the main challenges and solutions of SSB applications. We demonstrate ultra-fine pitch SSB process capability with 0.6 mil Au wire using newly developed response-based processes for sub-20 nm node wafer technology.


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