High Density, Tall Cu Pillars for 3D Packaging

2017 ◽  
Vol 2017 (1) ◽  
pp. 000346-000352
Author(s):  
Tom Swarbrick ◽  
Kevin Martin ◽  
Kousuki Mori
Keyword(s):  
Liquid Film ◽  
Mobile Applications ◽  
High Density ◽  
Electronic Components ◽  
Integration Approach ◽  
Cu Pillar ◽  
Pillar Diameter ◽  
3D Packaging ◽  
Negative Tone ◽  
3D Package

Abstract With demands for shrinking footprints and increasing I/O of electronic components, there is an increasing interest in electrodeposited Cu pillar structures for Package on Package (PoP) interconnects. One example of interest involves a 3D package integration approach with the memory mounted above the processor for mobile applications. This paper will explore the processes required and discuss the challenges for Cu pillar fabrication of PoP interconnects at sub 100um pitches. The test vehicles will include variables such as pillar diameter and pitch for a 200um thick liquid film negative tone plating resist on a 300mm wafer format. The high-density pillar pitch is expected to present challenges to resist material applications, lithography capability, and plating capability. Work for this paper is supported by major material and tool suppliers for resist materials, lithography tools, and plating chemistries & plating tools. JSR Micro, Rudolph Technologies, Atotech

Development of High Density RDL Technologies for Panel Level Processing

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000284-000313
Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Density ◽  
Organic Films ◽  
High Yield ◽  
Wafer Level ◽  
Final Size ◽  
Process Yield ◽  
Cu Pillar ◽  
Thin Organic Films ◽  
Advanced Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001555-001595
Author(s):  
Cornelia Tsang ◽  
Janet Okada ◽  
Eric Huenger
Keyword(s):  
Printed Circuit Boards ◽  
Process Integration ◽  
Product Yield ◽  
Wafer Surface ◽  
Wafer Level ◽  
Design Elements ◽  
Conformal Coating ◽  
3D Packaging ◽  
Study Process ◽  
Negative Tone

As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used in MEMs, printed circuit boards, backside vias, etc, and can play a significant role in enabling new 3D packaging solutions. In this research, the successful fabrication of an Optochip silicon interposer, which integrates electrical and optical components onto a single substrate with high density interconnection, was enabled through use of electrodeposited (ED) photoresist. The Optochip interposer was manufactured in a standard 200 mm semiconductor fab and this precipitated the process integration requirement of first etching “optical vias” into the silicon at wafer-level prior to the final lithography steps. As such, challenging topography was introduced into the system. A resist solution able to address the following conditions was required: 1) sufficient conformal coating into large optical vias measuring 150 um diameter by 200 um depth, 2) no resist pull-back over sharp 90 degree angle corners where the optical vias met the wafer surface, 3) ability to resolve 30 um diameter surface pads at 50 um pitch and 4) chemical resistance to Ni and cyanide-based Au plating baths. This presentation will discuss how various photoresists were examined that resulted in ED photoresist being chosen for the aforementioned application. Both negative-tone and positive-tone ED photoresists were considered. Experiments to study process parameters and environmental factors on product yield were performed using test wafers with optical vias. These experiments resulted in positive-tone ED photoresist being selected. Test wafers plated with NiAu resulted in ~ 90% process yield. The presentation will conclude by demonstrating the ability to achieve good yield on integrated product wafers.

3D Packaging Solution Providing DDR & LPDDR Co-Support for Ultrabooks and Next Generation Servers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002285-002315
Author(s):  
Simon McElrea ◽  
Vern Solberg
Keyword(s):  
High Performance ◽  
Electronic Systems ◽  
Reliability Modeling ◽  
Wire Bond ◽  
3D Packaging ◽  
Bond Interface ◽  
Improved Performance ◽  
3D Stacking ◽  
Process Complexity ◽  
3D Package

Effective 3D stacking of DRAM devices can offer many benefits; improved performance, increased component density and greater surface area utilization. To enable the new generations of processors to reach their performance potential many manufacturers have developed more efficient interface formats that enable greater memory bandwidth. This revolution in performance driven electronic systems continues to challenge the IC packaging industry. The challenge is clear. To ensure that the memory functions are able to support the increased signal speed, product developers will need to explore more innovative 3D package assembly techniques and process refinement methodologies. The methodology selected for package assembly, however, must consider process complexity, the costs associated with each process, overall package assembly yield and, from the users perspective, end product reliability. For some applications companies have had limited success in stacking die elements directly onto an interposer substrate using wire-bond processes. High performance DRAM die, however, is especially difficult to stack. This is due to the center positioned wire-bond sites. This factor has complicated the DRAM die stacking process and because of the excessively long wire-bond interface, functional signal speed is significantly degraded. Stacking individually packaged DRAM (package-on-package) has had considerable success but the package outline dimension and package height can be excessive. In this paper the authors will introduce a very innovative and very thin 3D package developed specifically for center-bond pad DRAM die. The package assembly methodology promises to remain economical because it requires no special die level process steps and it can utilize the existing package assembly infrastructure. Additionally, data compiled during extensive performance and reliability modeling will be presented along with the results from actual physical qualification testing.

Epoxy Underfill Challenges for Copper (Cu) Pillar Solder Bump Packages

2014 ◽  
Vol 2014 (1) ◽  
pp. 000247-000250
Author(s):  
Brian Schmaltz ◽  
Yukinari Abe ◽  
Kazuyuki Kohara
Keyword(s):  
Thermal Cycling ◽  
Solder Ball ◽  
Solder Bump ◽  
High Density ◽  
Lead Free ◽  
Reflow Process ◽  
Stress Concentrations ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

From Eutectic, to Lead Free, to Copper Pillar (Cu) Bumping Technologies. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder ball reflow process is being pushed by advancements in copper pillar capped bumps, which in turn allows for high density lead free IO counts at sub 40um bump pitches. Even so, low CTE epoxy materials are still needed in order to dissipate stress concentrations seen during thermal cycling. What challenges await this next technological revision? This presentation will centralize around the latest advancements in epoxy materials for Advanced Packaging Technology; Capillary Underfill (CUF) for narrow pitch Lead Free Copper (Cu) Pillar Solder Bump packages.

Assessment of Some Integrated Cooling Mechanisms for an Active IPEM

2004 ◽  
Author(s):  
Y. Pang ◽  
E. Scott ◽  
J. D. van Wyk ◽  
Z. Liang
Keyword(s):  
Power Electronics ◽  
Thermal Management ◽  
Three Dimensional ◽  
The Other ◽  
Other Hand ◽  
3D Packaging ◽  
3D Package

With the growing demands on the performance, cost, and advances in packaging and interconnection technology, three-dimensional (3D) packaging provides higher density packaging. On the other hand, thermal management of the 3D package becomes a very important issue. This paper assesses the various possibilities of integrated thermal management for integrated power electronics modules (IPEMs).

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