A Novel Conditioning Circuit for Floating-Gate ISFET Bio-Sensor

Floating-Gate-Ions-Sensitive-Field-Effect-Transistors (FG-ISFETs) are becoming the sensor’s platform for various fields such as biomedical and chemical sensors. Despite many advantages like quick response, small size as well as wide measurement range, the efficiency of the output measurement is widely affected by temperature, This requires more safety in the measured results and the analysis’s tools. This study describes a novel integrated circuit that improves the thermal stability of the output signal of the ion-sensitive field effect transistors (ISFETs). After that, we investigate the temperature dependency of the FG-ISFET using the mentioned macro model and we shows that the temperature coefficient is about of 6 mV/°C. Afterward, a new integrated interface circuit that can perform great temperature compensation was developed. This operation aims to enhance stability of readout circuit for FG-ISFET. The achieved result of the FG-ISFET under different simulations shows that the readout circuit has a good temperature compensation i.e. :2.4 〖10〗^(-9) mV/°C.

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Temperature Compensation Circuit for ISFET Sensor

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea10010002 ◽

2020 ◽

Vol 10 (1) ◽

pp. 2 ◽

Cited By ~ 2

Author(s):

Ahmed Gaddour ◽

Wael Dghais ◽

Belgacem Hamdi ◽

Mounir Ben Ali

Keyword(s):

Integrated Circuit ◽

Temperature Compensation ◽

Field Effect ◽

Field Effect Transistors ◽

Aqueous Samples ◽

Single Chip ◽

Compensation Circuit ◽

Ph Measurements ◽

Ph Values ◽

Effect Transistor

PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. To achieve this purpose, the considered ISFET macro model is analyzed and validated with experimental data. Moreover, we investigate the temperature dependency on the voltage-current (I-V). Accordingly, an improved conditioning circuit is designed in order to reduce the temperature sensitivity on the measured pH values of the ISFET sensor. The numerical validation results show that the developed solution accurately compensates the temperature variation on the measured pH values at low power consumption.

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Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽

10.3390/en13010187 ◽

2020 ◽

Vol 13 (1) ◽

pp. 187 ◽

Cited By ~ 1

Author(s):

Kamil Bargieł ◽

Damian Bisewski ◽

Janusz Zarębski

Keyword(s):

Silicon Carbide ◽

Integrated Circuit ◽

Field Effect ◽

Field Effect Transistors ◽

Dynamic Properties ◽

Modified Model ◽

Spice Model ◽

Capacitance Voltage ◽

Effect Transistor ◽

Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

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Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.527 ◽

2016 ◽

Vol 13 (4) ◽

pp. 143-154 ◽

Cited By ~ 4

Author(s):

Jim Holmes ◽

A. Matthew Francis ◽

Ian Getreu ◽

Matthew Barlow ◽

Affan Abbasi ◽

...

Keyword(s):

High Temperature ◽

Integrated Circuits ◽

Integrated Circuit ◽

Field Effect ◽

Field Effect Transistors ◽

Logic Synthesis ◽

Oxide Semiconductor ◽

Cmos Process ◽

Timing Models ◽

High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Thin Film FETs: Exploring the Performance Limit of Carbon Nanotube Network Film Field‐Effect Transistors for Digital Integrated Circuit Applications (Adv. Funct. Mater. 16/2019)

Advanced Functional Materials ◽

10.1002/adfm.201970106 ◽

2019 ◽

Vol 29 (16) ◽

pp. 1970106

Author(s):

Chenyi Zhao ◽

Donglai Zhong ◽

Jie Han ◽

Lijun Liu ◽

Zhiyong Zhang ◽

...

Keyword(s):

Thin Film ◽

Carbon Nanotube ◽

Integrated Circuit ◽

Field Effect ◽

Field Effect Transistors ◽

Performance Limit ◽

Carbon Nanotube Network ◽

Digital Integrated Circuit

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Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽

10.3390/mi11090852 ◽

2020 ◽

Vol 11 (9) ◽

pp. 852

Author(s):

Jong Hyeok Oh ◽

Yun Seop Yu

Keyword(s):

Integrated Circuit ◽

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistors ◽

Electrical Coupling ◽

Propagation Delay ◽

Channel Length ◽

Memory Window ◽

Switching Voltage ◽

Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

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