scholarly journals Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 852
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Propagation Delay ◽  
Channel Length ◽  
Memory Window ◽  
Switching Voltage ◽  
Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors

2021 ◽  
Vol 21 (8) ◽  
pp. 4293-4297
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Threshold Voltage ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Memory Window ◽  
Electrical Characteristics ◽  
Logic Device ◽  
Interlayer Dielectric

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.

scholarly journals Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

2020 ◽  
Vol 11 (1) ◽  
pp. 277
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
3 Dimensional ◽  
Noise Margin ◽  
Type Transistor

In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as TILD decreases and they increase as Lg increases, and thus there is a strong coupling in M3INV at the range of TILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same TILD and Lg. The switching threshold voltage (Vm) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the Vm variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of Vm, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.

Inverter design with positive feedback field-effect transistors

2021 ◽  
Author(s):  
Changhoon Lee ◽  
Changwoo Han ◽  
Changhwan Shin
Keyword(s):  
Positive Feedback ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Feedback Mechanism ◽  
Silicon On Insulator ◽  
Logic Device ◽  
Device Applications ◽  
Positive Feedback Mechanism ◽  
Switching Devices

Abstract As the physical size of semiconductor devices continues to be aggressively scaled down, feedback field-effect transistors (FBFET) with a positive feedback mechanism among a few promising steep switching devices have received attention as next-generation switching devices. Conventional FBFETs have been studied to explore their device performance. However, this has been restricted to the case of single FBFET; basic circuit designs with FBFETs have not been investigated extensively. In this work, we propose an inverter circuit design with silicon-on-insulator (SOI) FBFETs; we verified this inverter design with mixed-mode technology computer-aided design simulation. The basic principles and mechanisms for designing FBFET inverter circuits are explained because their configuration is different from conventional inverters. In addition, the device parameters necessary to optimize circuit construction are introduced for logic device applications.

scholarly journals Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yejin Yang ◽  
Young-Soo Park ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Drain Current ◽  
Memory Window ◽  
Interface Trap ◽  
Electrical Characteristics ◽  
The Difference ◽  
Trap Charges

AbstractIn this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

scholarly journals Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 187 ◽  
Author(s):  
Kamil Bargieł ◽  
Damian Bisewski ◽  
Janusz Zarębski
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Dynamic Properties ◽  
Modified Model ◽  
Spice Model ◽  
Capacitance Voltage ◽  
Effect Transistor ◽  
Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

scholarly journals Impact of the channel length on molybdenum disulfide field effect transistors with hafnia-based high-k dielectric gate

AIP Advances ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 065229
Author(s):  
Yanxiao Sun ◽  
Gang Niu ◽  
Wei Ren ◽  
Jinyan Zhao ◽  
Yankun Wang ◽  
...  
Keyword(s):  
Molybdenum Disulfide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Channel Length ◽  
High K ◽  
High K Dielectric

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

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