scholarly journals Analysis of Low Power and High Speed Double Tail Comparator Using Gnrfet Technology

2021 ◽  
Vol 23 (06) ◽  
pp. 1649-1665
Author(s):  
Vineet Dubey ◽  
◽  
Dr. Imran ◽  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Graphene Nanoribbons ◽  
Time Frame ◽  
Oxide Semiconductor ◽  
Open Door ◽  
Cmos Inverter ◽  
Line Region ◽  
Initial Texture ◽  
Component Time

Moore’s guideline has been a fundamental benchmark for patterns in the locale of microelectronics and measurements preparing. It has played an instrumental position in driving the part financial aspects and downsizing of the component time frame has been the major system for improving the general execution of the gadget. in any case, as we hold to diminish, close to the nanometre routine, various elements like line region unpleasantness, burrowing outcomes, arbitrary dopant changes, fast channel results, and numerous others have a tendency to impact its working and thereupon, its rise as of intense quintessence to investigate other open door substances that may help intensify the soaking Moore’s guideline. some of the research is as of now going inside the zone and numerous open door advances like CNFETs, FINFETs, GNRFETs. Region sway transistors the utilization of Graphene Nano-Ribbons (GNRFETs) has developed as promising innovation as a result of their stunning supplier transport homes and capacity for huge scale preparing and creation. This paper investigates the GNRFETs inverter generally speaking execution with CMOS inverter at 32nm time hub. Reproductions recommend about 2.5x upgrades inside the proliferation dispense with and 2x enhancements inside the quality put-off item (PDP). what’s more improvement of results was gotten through different the kind of Nano-Ribbons together with the convey voltage. On different the broad kind of nano-ribbons, it has turned out to be set that, spread put off reductions, at the indistinguishable time as powerful power utilization will increment. principally based definitely at the derivation, the upgraded outcome altered into chose to be 15 nano-ribbon. The outcomes imply that that GNRFET is a promising open door for Si-CMOS, making it a splendid recommendation to help intensify soaking Moore’s law. Graphene is an exciting new fabric with radiant electric properties, for the most part inside the state of graphene nanoribbons. on this educational document, we inspect steel-oxide-semiconductor and graphene nanoribbon discipline- impact transistors and recommend the proceeded with utilization of MOSFETs through 2023. This archive fills in as a top-notch initial texture for people with a legacy in semiconductors who want to find out about graphene and GNRFETs.

scholarly journals A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

2018 ◽  
Vol 170 ◽  
pp. 01006 ◽  
Author(s):  
Laurent A. Francis ◽  
Amor Sedki ◽  
Nicolas André ◽  
Valéria Kilchytska ◽  
Pierre Gérard ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect Transistors ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
High Dose ◽  
Partial Recovery ◽  
Proton Radiation ◽  
Cmos Inverter ◽  
Inversion Point

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

2019 ◽  
Vol 28 (10) ◽  
pp. 1950165 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Power Reduction ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Maximum Delay ◽  
Average Power Consumption

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

scholarly journals Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

2019 ◽  
Vol 9 (1) ◽  
pp. 5962-5965
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
High Speed ◽  
Peak Power ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Addressable Memory ◽  
Power Peak ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

scholarly journals Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

2021 ◽  
Vol 7 (1) ◽  
pp. 18-29
Author(s):  
Vinod Pralhad Tayade ◽  
Swapnil Laxman Lahudkar
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
20 Nm ◽  
Graphene Material

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

scholarly journals The Mixed Logic Style based Low Power and High Speed 3-2 Compressor for ASIC designs at 32nm Technology

2019 ◽  
Vol 9 (1) ◽  
pp. 43-49
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Logic Design ◽  
Average Power Consumption

Compressors are the fundamental building blocks to construct Data Processing arithmetic units. A novel 3-2 Compressor is presented in this paper which is designed by Mixed logic design style. In addition to small size transistors and reduced transistor activity compared to conventional CMOS (Complementary Metal Oxide Semiconductor) gates, it provides the priority between the High logic and Low logic for the computation of the output. Various logic topologies are used to design the 3-2 compressor like High-Skew(Hi-Skew), Low-Skew(Li-Skew), TGL (Transmission Gate Logic) and DVL (Dual value Logic). This new approach gives the better operating speed, low power consumption compared to conventional logic design by reducing the transistors activity, improving the driving capability and reduced input capacitance with skew gates. Especially the Mixed logic style-3 provides 92.39% average power consumption and Propagation Delay of 99.59% at 0.8v. The H-SPICE simulation tool is used for construction and evaluation of compressor logic at different voltages. 32nm model file is used for MOS transistors

scholarly journals Design of High-Speed Low Power Computational Blocks for DSP Processors

2021 ◽  
Vol 11 (2) ◽  
pp. 1419-1429
Author(s):  
Alivelu Manga N.
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Digital Signal ◽  
Oxide Semiconductor ◽  
Performance Criteria

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

scholarly journals Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

2019 ◽  
Vol 9 (3) ◽  
pp. 21 ◽  
Author(s):  
Satheesh Kumar S ◽  
Kumaravel S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Energy ◽  
Oxide Semiconductor ◽  
High Energy Particle ◽  
Single Event Upset ◽  
Single Event ◽  
Clock Gating

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature.

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