scholarly journals Revisiting Analytical Models of N-Type Symmetric Double-Gate MOSFETs Shaded Conditions

2020 ◽  
Vol 24 (1) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Prabir Saha
Keyword(s):  
Integrated Circuits ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Cmos Technology ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects

Nowadays, the endlessly increasing demand for faster and complex integrated circuits (IC) has been fuelled by the scaling of metal-oxide-semiconductor field-effect-transistors (MOSFET) to smaller dimensions. The continued scaling of MOSFETs approaches its physical limits due to short-channel effects (SCE). Double-gate (DG) MOSFET is one of the promising alternatives as it offers better immunity towards SCEs and can be scaled to the shortest channel length. In future, ICs can be designed using DG-CMOS technology for which mathematical models depicting the electrical characteristics of the DG MOSFETs are foremost needed. In this paper, a review on n-type symmetric DG MOSFETs models has been presented based on the analyses of electrostatic potential distribution, threshold voltage, and drain-current models. Mathematical derivations of the device models are described elaborately, and numerical simulations are also carried out to validate the replicability of models.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Impact of Variation of Device Parameters on the Electrical Characteristics of Double-Gate Mosfets

2020 ◽  
Vol 9 (3) ◽  
pp. 3658-3661
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Channel Effects ◽  
Circuits Vlsi ◽  
Logical Functions

Very large scale integrated circuits (VLSI) have been possible owing to the shrinking of metal-oxide semiconductor field-effect transistors (MOSFETs). By reducing the dimensions of the device it is possible to have high density on the chip. This increases the number of logical functions that can be implemented on a given dimension of the chip. Along with the advantages associated with the shrinking of the devices, it also has certain drawbacks commonly known as short-channel effects. Due to these effects, device characteristics deviate from its expected values. There are many techniques through which these deviations can be minimized. One of the promising and highly researched techniques these days is the use of Multi-gate (MG) transistors in VLSI. Double-gate (DG) transistor is one among MG transistors. In DG MOSFET, substrate is surrounded by gates from two opposite sides. This leads to more control over the channel electrons by the gate terminals. In this paper, the consequence of change of various device constraints on the electrical characteristics of the DG MOSFETs will be investigated. Through the results, one can know to what extent the electrical properties changes when the dimensions and/or material properties are changed. This will be very helpful in determining the maximum current associated with those dimensions of DG MOSFETs.

Examining the Short Channel Characteristic and Performance of Triple Material Double Gate Silicon-on-Nothing Metal Oxide Semiconductor Field Effect Transistors with Grading Channel Concentration

2019 ◽  
Vol 14 (12) ◽  
pp. 1672-1679 ◽  
Author(s):  
Ningombam Ajit Kumar ◽  
Aheibam Dinamani Singh ◽  
Nameirakpam Basanta Singh
Keyword(s):  
Surface Potential ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel Effects ◽  
Parabolic Approximation ◽  
Short Channel ◽  
Channel Characteristic ◽  
Channel Effects ◽  
And Performance

A 2D surface potential analytical model of a channel with graded channel triple material double gate (GCTMDG) Silicon-on-Nothing (SON) MOSFET is proposed by intermixing the benefits of triple material in gate engineering and graded doping in the channel. The surface potential distribution function of the GCTMDG SON MOSFET is obtained by solving the Poisson's equation, applying suitable boundary conditions, and using a parabolic approximation method. It is seen in the proposed device that the Short Channel Effects (SCEs) are subdued due to the apprehensible step in the surface potential profile that screen the potential of the drain. The effects of the various device parameters are studied to check the merit of the device. For the validation of the proposed device, it is compared with the simulated results of ATLASTM, a device simulator from SILVACO.

scholarly journals Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019 ◽  
Vol 8 (2S6) ◽  
pp. 783-791
Keyword(s):  
Field Effect Transistors ◽  
Scaling Limit ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Length Variation ◽  
Gate Length ◽  
Double Gate ◽  
Simulation Design ◽  
Short Channel ◽  
Fully Depleted

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg ) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs

2016 ◽  
Vol 3 (3) ◽  
Author(s):  
Chunsheng Jiang ◽  
Renrong Liang ◽  
Jing Wang ◽  
Jun Xu
Keyword(s):  
Electrostatic Potential ◽  
Numerical Solutions ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Analytical Models ◽  
Short Channel ◽  
Surrounding Gate ◽  
Silicon And Germanium

AbstractWhen the traditional planar metal-oxide-semiconductor-field-effect transistors (MOSFETs) encounter insurmountable bottleneck of static power dissipation, junctionless transistor (JLT) becomes a promising candidate for sub-22 nm nanoscale devices due to its simpler fabrication process and better short-channel performances. Subthreshold behaviors dominate the standby power of nanoscale JLTs. In this chapter, a physics-based analytical model of electrostatic potential for both silicon and germanium short-channel junctionless cylindrical surrounding-gate (JLCSG) MOSFETs operated in the subthreshold regime is proposed, in which the full twodimensional (2D) Poisson’s equation is solved in the channel region by a method of series expansion. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this result, the expressions of threshold voltage, subthreshold drain current, and subthreshold swing for JLCSG MOSFETs are derived. Subthreshold behaviors are studied in detail by changing different device parameters and bias conditions, including doping concentration, channel radius, gate length, gate equivalent oxide layer thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the three-dimensional simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLCSG MOSFETs and to optimize their device performances.

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