Design of a low-power high open-loop gain operational amplifier for capacitively-coupled instrumentation amplifiers

2017 ◽  
Vol 45 (11) ◽  
pp. 1552-1575 ◽  
Author(s):  
Pakorn Prasopsin ◽  
Woradorn Wattanapanitch
2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000305-000309 ◽  
Author(s):  
Vinayak Tilak ◽  
Cheng-Po Chen ◽  
Peter Losee ◽  
Emad Andarawis ◽  
Zachary Stum

Silicon carbide based ICs have the potential to operate at temperatures exceeding that of conventional semiconductors such as silicon. Silicon carbide (SiC) based MOSFETs and ICs were fabricated and measured at room temperature and 300°C. A common source amplifier was fabricated and tested at room temperature and high temperature. The gain at room temperature and high temperature was 7.6 and 6.8 respectively. A SiC MOSFET based operational amplifier was also fabricated and tested at room temperature and 300°C. The small signal open loop gain at 1kHz was 60 dB at room temperature and 57 dB at 300°C. Long term stability testing at 300°C of the MOSFET and common source amplifiers showed very little drift.


2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000109-000112
Author(s):  
Cheng-Po Chen ◽  
Lucian Stoica ◽  
Emad Andarawis ◽  
Russell Simpson

Abstract A custom designed SOI operational amplifier (opamp) is used in two application circuits and characterized up to 300°C: 1. An instrumentation amplifier (in-amp) with a differential voltage gain of 100, and 2. A transimpedance amplifier (TIA) with a gain of 1.2 giga Ohm, used to sense picoamp level signals. The opamp operates with a 5-volt supply, and has rail-to-rail inputs and outputs. The open loop gain of the opamp is about 100 dB at room temperature and stays above 60 dB at 300°C. The in-amp uses the classic three operational amplifier (opamp) architecture with off-chip feedback resistors. The closed loop gain of the in-amp remains stable at 100, up to 250°C, and drops to 95 at 300°C. Temperature dwell test shows the in-amp maintaining stable functionality at 300°C for at least 1000 hours. The TIA also incorporates a silicon carbide diode to achieve gain compression by lowering the feedback gain when the input signal is higher, thus allowing a higher dynamic range input before the circuit output saturates.


2013 ◽  
Vol 380-384 ◽  
pp. 3304-3307
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai

In this paper, an operational amplifier with low-power consumption has been designed. Using the complementary differential pair for the input stage and the class AB structure for the output stage, the common-mode input range and output swing of the proposed circuit could achieved rail-to-rail. Based on TSMC 0.18μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 300μw. The circuit's phase margin is 68 degrees, CMRR is 135dB and power supply rejection ratio is 63dB.


2019 ◽  
Vol 8 (4) ◽  
pp. 1802-1808

The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.


2013 ◽  
Vol 380-384 ◽  
pp. 3283-3286
Author(s):  
Lin Hai Cui ◽  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong

A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.


2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.


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