Development of Low Power Cryogenic Readout Integrated Circuits Using Fully-Depleted-Silicon-on-Insulator CMOS Technology for Far-Infrared Image Sensors

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

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Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature

Sensors ◽

10.3390/s18072338 ◽

2018 ◽

Vol 18 (7) ◽

pp. 2338 ◽

Cited By ~ 1

Author(s):

Laurent Artola ◽

Ahmad Youssef ◽

Samuel Ducret ◽

Franck Perrier ◽

Raphael Buiron ◽

...

Keyword(s):

Integrated Circuits ◽

Cryogenic Temperature ◽

Infrared Image ◽

Image Sensors ◽

Radiation Hardness ◽

Single Event ◽

Readout Integrated Circuit ◽

Flip Flop ◽

Single Event Effects ◽

Infrared Image Sensors

This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K. The analyses of the experimental data are completed using the SEE prediction tool MUSCA SEP3. The conclusions derived from the experimental measurements and related analyses allow to update the current SEE radiation hardness assurance (RHA) for readout integrated circuits of infrared image sensors used at cryogenic temperatures. The current RHA update is performed on SEE irradiation tests at room temperature, as opposed to the operational cryogenic temperature. These tests include SET (Single Event Transient), SEU (Single Event Upset) and SEFI (Single Event Functional Interrupt) irradiation tests. This update allows for reducing the cost of ROIC qualifications and the test setup complexity for each space mission.

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078720001087 ◽

2020 ◽

pp. 1-18

Author(s):

Florent Torres ◽

Eric Kerhervé ◽

Andreia Cathelin ◽

Magali De Matos

Keyword(s):

Power Amplifier ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Fully Depleted ◽

Technology Roadmap ◽

Wide Range ◽

28 Nm ◽

Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

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