Electrical properties of metal-piezoelectric semiconductor interface under stress

1978 ◽  
Vol 78 (1) ◽  
pp. 209-219 ◽  
Author(s):  
M. Kusaka
2016 ◽  
Vol 858 ◽  
pp. 697-700 ◽  
Author(s):  
Tomasz Sledziewski ◽  
Heiko B. Weber ◽  
Michael Krieger

In this work the effect of phosphorus on the electrical properties of n-type 4H-SiC MOS capacitors is studied. Phosphorus ions are implanted into the epitaxial layers prior to the deposition of SiO2 by PECVD, in shallow depths and at concentrations at the oxide-semiconductor interface in the range of (5 x 1017…1 x 1019) cm-3. Those samples are compared with 31P-implanted 4H-SiC MOS capacitors with thermally grown oxides, which were primarily investigated in the previous work of the authors. It is shown that independently of the oxide technology phosphorus may lead to decrease of the density of interface traps, whose response time to the AC voltage is longer than 1 µs. The side-effect of the implantation of phosphorus is generation of the very fast interface states, which are able to follow the frequencies over 1 MHz.


2018 ◽  
Vol 924 ◽  
pp. 931-934
Author(s):  
Tobias Erlbacher ◽  
Andreas Huerner ◽  
Yi Lin Zhu ◽  
Linh Bach ◽  
Andreas Schletz ◽  
...  

Schottky diodes fabricated on free-standing B doped monocrystalline diamond substrate have been investigated. As expected, reverse leakage current due to Schottky barrier lowering has been observed due to the high electric field at the metal-semiconductor interface. Forward current is highest under operating temperatures between 400 and 450K due to incomplete ionization hole mobility dependence on temperature. It is demonstrated that the static device characteristics in the temperature range from 300K to 450K can be modelled by parametrizing an analytical introduced for unipolar SiC and Si diodes.


1996 ◽  
Vol 448 ◽  
Author(s):  
E. Kamińska ◽  
A. Piotrowska ◽  
S. Kasjaniuk ◽  
S. Gierlotka

AbstractThe relationship between electrical properties and microstructure of pure Zn and Au(Zn) contacts to p-GaAs has been studied. Thermally activated changes in ФB correlate with structural processes at MS interfaces. For Zn/GaAs contacts, lowering of ФB from 0.63 eV to 0.35 eV corresponds to the penetration of Zn into the native oxide layer. In AuZn/p-GaAs contacts, β-AuZn phase is responsible for the formation of ФB=0.4 eV in as-deposited contacts. The onset of the ohmic behaviour of Au(Zn)/p-GaAs contacts (ФB=0.3 eV) coincides with the appearance of α3-AuZn phase for Zn content less than 20 at.% or α1-AuZn, for higher Zn concentrations.The obtained results prove that the mechanism responsible for the formation of low-resistance Zn -based contacts to p-type GaAs is associated with the lowering of the Schottky barrier at the metal/semiconductor interface. We suggest that the ultimate properties of these contacts are determined by the presence of a single, specific phase in a direct contact with the semiconductor.


2020 ◽  
Vol 8 (45) ◽  
pp. 16057-16066
Author(s):  
Fangpei Li ◽  
Wenbo Peng ◽  
Zijian Pan ◽  
Yongning He

The coupling effect at the two piezoelectric semiconductor interface can be designed to largely improve device photoresponse performances.


2009 ◽  
Vol 4 (2) ◽  
pp. 79-83
Author(s):  
R. Zandonay ◽  
R. G. Delatorre ◽  
A. A. Pasa

Schottky diodes were prepared by photoinduced electrodeposition of Co on p-Si, probing the influence of different concentrations of CoSO4 (26 and 104 mM) in the electrolyte on the electrical properties of the metal-semiconductor interface. Current density versus voltage (JxV) and capacitance versus voltage (CxV) measurements were performed in diodes with different Co thicknesses to obtain the barrier heights and ideality factors. Atomic force microscopy (AFM) and vibrating sample magnetometry (VSM) were additional techniques used to determine the surface morphology and the magnetic response. Devices with improved electrical properties were observed by increasing the thickness of the metal, i. e., saturation currents with values of about 0.1 mA.cm-2, ideality factors close to 1.19 and barrier heights of about 0.65 eV were determined.


Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


Author(s):  
J.P.S. Hanjra

Tin mono selenide (SnSe) with an energy gap of about 1 eV is a potential material for photovoltaic applications. Various authors have studied the structure, electronic and photoelectronic properties of thin films of SnSe grown by various deposition techniques. However, for practical photovoltaic junctions the electrical properties of SnSe films need improvement. We have carried out investigations into the properties of flash evaporated SnSe films. In this paper we report our results on the structure, which plays a dominant role on the electrical properties of thin films by TEM, SEM, and electron diffraction (ED).Thin films of SnSe were deposited by flash evaporation of SnSe fine powder prepared from high purity Sn and Se, onto glass, mica and KCl substrates in a vacuum of 2Ø micro Torr. A 15% HF + 2Ø% HNO3 solution was used to detach SnSe film from the glass and mica substrates whereas the film deposited on KCl substrate was floated over an ethanol water mixture by dissolution of KCl. The floating films were picked up on the grids for their EM analysis.


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