Process development and simulation of glucose isomerase production from birchwood xylan by a Streptomycetes fusant

1998 ◽  
Vol 1 (2) ◽  
pp. 159-168 ◽  
Author(s):  
Siriluk Teeradakorn ◽  
Michimasa Kishimoto ◽  
Tatsuji Seki ◽  
Pairoh Pinphanichakarn ◽  
Toshiomi Yoshida
Keyword(s):  
Process Development ◽  
Glucose Isomerase ◽  
Birchwood Xylan

Advanced TEM sample preparation techniques for submicron Si devices

1995 ◽  
Vol 53 ◽  
pp. 516-517 ◽  
Author(s):  
P. B. Basham ◽  
H. L. Tsai
Keyword(s):  
Sample Preparation ◽  
Process Development ◽  
Light Transmission ◽  
Specific Area ◽  
Turnaround Time ◽  
Small Hole ◽  
Area Of Interest ◽  
Transmission Electron ◽  
Polished Side ◽  
Preparation Techniques

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

LAS TIC COMO HERRAMIENTAS EN EL PROCESO DE ENSEÑANZA - APRENDIZAJE PARA OPTIMIZAR EL RENDIMIENTO ACADÉMICO.

2015 ◽  
Vol 3 (1) ◽  
Author(s):  
Fernando Pacheco Olea ◽  
Carolina Villacís ◽  
Patricio Álvarez Muñoz
Keyword(s):  
Academic Performance ◽  
Information And Communication Technologies ◽  
Process Development ◽  
Educational Process ◽  
Learning Tools ◽  
New Information ◽  
Training Plan ◽  
Nuevas Tecnologías ◽  
Information And Communication ◽  
Technological Tool

Este artículo es producto de una investigación que tiene como finalidad establecer la relación que tienen las TIC con el rendimiento académico de los estudiantes del Colegio Técnico Industrial “La Alborada” de la ciudad de Milagro, provincia del Guayas, Ecuador. Este estudio se enmarca dentro de las investigaciones descriptivas, correlacionales, ya que por medio del análisis, observación, comparación y descripción de las variables, se establece el escaso uso de las herramientas tecnológicas en el proceso educativo. Los datos estadísticos se obtienen de los resultados por la aplicación de instrumentos a los estudiantes y docentes de la institución. Se utilizaron los métodos deductivos, inductivos y teóricos para el desarrollo del proceso. La propuesta requiere un fortalecimiento en el uso de las nuevas tecnologías de la Información y Comunicación, siendo importante que los docentes conozcan el uso adecuado de las mismas y las integren en sus horas de clases, porque mejorará el rendimiento académico de los estudiantes por su nueva forma de explicar las clases que serán más interactivas y divertidas. Es necesario realizar un Plan de capacitación en el uso de las herramientas e- learning que garantice una educación de calidad.   Palabras claves: TIC, rendimiento académico, proceso educativo.   ABSTRACT   This article is the result of a research that aims to establish the relationship of ICTs to academic performance of students in the Industrial Technical College “La Alborada” in Milagro, Guayas, Ecuador. This study is part of a descriptive, correlational research, since through analysis, observation, comparison and description of the variables, the limited use of technological tool sin the educational process is established. The statistics are obtained from the resultsof the application of tools for students and teachers of the institution. Deductive, inductive and theoretical process development methods were used. The proposal requires as treng then ing in the use of new information and communication technologies and it is important that teachers become aware of their proper use and incorporate them in their classes, because these will improve the academic performance of students in classes that are more interactive and fun. It’s necessary to design a training plan in the use ofe-learning tools to ensure quality education.   Keywords: TIC, academic achievement, educational process.   Recibido: febrero 2015Aprobado: mayo 2015

Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

2001 ◽  
Author(s):  
DongKwon Jeong ◽  
JuHyeon Ahn ◽  
SangIn Lee ◽  
JooHyuk Chung ◽  
ByungLyul Park ◽  
...  
Keyword(s):  
Process Improvement ◽  
Process Development ◽  
Metal Corrosion ◽  
Pass Rate ◽  
Design Rule ◽  
The Novel ◽  
Corrosion Loss ◽  
Barrier Metal ◽  
Development State ◽  
Failure Types

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

Local Lattice Strain Measurement Using Geometric Phase Analysis of Dark Field Images from Scanning Transmission Electron Microscopy

2011 ◽  
Author(s):  
Jayhoon Chung ◽  
Guoda Lian ◽  
Lew Rabenberg
Keyword(s):  
Phase Analysis ◽  
Geometric Phase ◽  
Process Development ◽  
Local Strain ◽  
Strain Engineering ◽  
Dark Field ◽  
Scanning Transmission Electron ◽  
Transmission Electron ◽  
Geometric Phase Analysis ◽  
Scanning Transmission

Abstract Since strain engineering plays a key role in semiconductor technology development, a reliable and reproducible technique to measure local strain in devices is necessary for process development and failure analysis. In this paper, geometric phase analysis of high angle annular dark field - scanning transmission electron microscope images is presented as an effective technique to measure local strains in the current node of Si based transistors.

X-Ray Nanotomography (XRMT) Tool for Non-Destructive High-Resolution Imaging of ICs

2001 ◽  
Author(s):  
Wenbing Yun ◽  
Steve Wang ◽  
David Scott ◽  
Kenneth W. Nill ◽  
Waleed S. Haddad
Keyword(s):  
High Resolution ◽  
Process Development ◽  
3D Visualization ◽  
Tomographic Reconstruction ◽  
Reconstruction Algorithms ◽  
X Ray ◽  
Visualization Software ◽  
Volumetric Reconstruction ◽  
Resolution Imaging ◽  
Non Destructive

Abstract A high-resolution table-sized x-ray nanotomography (XRMT) tool has been constructed that shows the promise of nondestructively imaging the internal structure of a full IC stack with a spatial resolution better than 100 nm. Such a tool can be used to detect, localize, and characterize buried defects in the IC. By collecting a set of X-ray projections through the full IC (which may include tens of micrometers of silicon substrate and several layers of Cu interconnects) and applying tomographic reconstruction algorithms to these projections, a 3D volumetric reconstruction can be obtained, and analyzed for defects using 3D visualization software. XRMT is a powerful technique that will find use in failure analysis and IC process development, and may facilitate or supplant investigations using SEM, TEM, and FIB tools, which generally require destructive sample preparation and a vacuum environment.

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