scholarly journals Van der Waals engineering of ferroelectric heterostructures for long-retention memory

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Xiaowei Wang ◽  
Chao Zhu ◽  
Ya Deng ◽  
Ruihuan Duan ◽  
Jieqiong Chen ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Memory Performance ◽  
Van Der Waals ◽  
Memory Cell ◽  
Single Pulse ◽  
Memory Retention ◽  
Metal Insulator ◽  
Limited Memory ◽  
Effect Transistor ◽  
Free Interfaces

AbstractThe limited memory retention for a ferroelectric field-effect transistor has prevented the commercialization of its nonvolatile memory potential using the commercially available ferroelectrics. Here, we show a long-retention ferroelectric transistor memory cell featuring a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals. Our device exhibits 17 mV dec−1 operation, a memory window larger than 3.8 V, and program/erase ratio greater than 107. Thanks to the trap-free interfaces and the minimized depolarization effects via van der Waals engineering, more than 104 cycles endurance, a 10-year memory retention and sub-5 μs program/erase speed are achieved. A single pulse as short as 100 ns is enough for polarization reversal, and a 4-bit/cell operation of a van der Waals ferroelectric transistor is demonstrated under a 100 ns pulse train. These device characteristics suggest that van der Waals engineering is a promising direction to improve ferroelectronic memory performance and reliability for future applications.

scholarly journals Investigating the Effects of Seizures on Procedural Memory Performance in Patients with Epilepsy

2021 ◽  
Vol 11 (2) ◽  
pp. 261
Author(s):  
Frank J. van Schalkwijk ◽  
Walter R. Gruber ◽  
Laurie A. Miller ◽  
Eugen Trinka ◽  
Yvonne Höller
Keyword(s):  
Temporal Lobe ◽  
Declarative Memory ◽  
Memory Performance ◽  
Total Sample ◽  
Learning Task ◽  
Procedural Memory ◽  
Memory Retention ◽  
Motor Sequence ◽  
Performance Improvements ◽  
Patients With Epilepsy

Memory complaints are frequently reported by patients with epilepsy and are associated with seizure occurrence. Yet, the direct effects of seizures on memory retention are difficult to assess given their unpredictability. Furthermore, previous investigations have predominantly assessed declarative memory. This study evaluated within-subject effects of seizure occurrence on retention and consolidation of a procedural motor sequence learning task in patients with epilepsy undergoing continuous monitoring for five consecutive days. Of the total sample of patients considered for analyses (N = 53, Mage = 32.92 ± 13.80 y, range = 18–66 y; 43% male), 15 patients experienced seizures and were used for within-patient analyses. Within-patient contrasts showed general improvements over seizure-free (day + night) and seizure-affected retention periods. Yet, exploratory within-subject contrasts for patients diagnosed with temporal lobe epilepsy (n = 10) showed that only seizure-free retention periods resulted in significant improvements, as no performance changes were observed following seizure-affected retention. These results indicate general performance improvements and offline consolidation of procedural memory during the day and night. Furthermore, these results suggest the relevance of healthy temporal lobe functioning for successful consolidation of procedural information, as well as the importance of seizure control for effective retention and consolidation of procedural memory.

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

2012 ◽  
Vol 52 (8) ◽  
pp. 1627-1631 ◽  
Author(s):  
Jer-Chyi Wang ◽  
Chih-Ting Lin ◽  
Chi-Hsien Huang ◽  
Chao-Sung Lai ◽  
Chin-Hsiang Liao
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Charge Storage ◽  
Data Retention ◽  
Retention Characteristics

The dual role of PZT in metal-PZT-Al2O3 structure for nonvolatile memory cell

2010 ◽  
Author(s):  
Sharon Cui ◽  
Dongseog Eun ◽  
Bozidar Marinkovic ◽  
Cheng-Yi Peng ◽  
Xiao Pan ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Dual Role

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

scholarly journals Low Power based Dynamic TSPC D flip flop for High Performance Applications

2020 ◽  
Vol 9 (8) ◽  
pp. 758-762
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Memory Cell ◽  
Research Center ◽  
Short Channel ◽  
Flip Flop ◽  
Force Application ◽  
Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

2013 ◽  
Vol 14 (5) ◽  
pp. 1231-1236 ◽  
Author(s):  
Min-Hoi Kim ◽  
Gyu Jeong Lee ◽  
Chang-Min Keum ◽  
Sin-Doo Lee
Keyword(s):  
Nonvolatile Memory ◽  
Memory Cell ◽  
Organic Inverter
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