scholarly journals Characteristics investigation on 4.5kV IGBT with partially narrow mesa and split-gate

2021 ◽  
Vol 300 ◽  
pp. 01012
Author(s):  
Xuebing Zhai ◽  
Tong Yang ◽  
Ruliang Zhang ◽  
Jiang Du

Low on-state voltage and low turn-off loss are key issues for IGBT used in HVDC and FACTS. Partial narrow mesa was introduced to improve emitter side contact resistance of IGBT based on Nakagawa limit assumption. However, turn-off loss increases and short circuit sustainability get worse. Split gate separates gate electrode from drift region and reduces gate-collector capacitance to lower turn-off energy loss. Combination partial narrow mesa with split gate can get better gate performance and turn-off characteristics in 4.5kV IGBT. Simulated results with TCAD show proposed models improves switching loss and gate reliability. By adjusting split gap electric filed, split gate shape has an important effect on turn-on characteristics.

2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


2011 ◽  
Vol 679-680 ◽  
pp. 722-725 ◽  
Author(s):  
Georg Tolstoy ◽  
Dimosthenis Peftitsis ◽  
Jacek Rabkowski ◽  
Hans Peter Nee

A 4.1x4.1mm2, 100mΩ 1,2kV lateral channel vertical junction field effect transistor (LCVJFET) built in silicon carbide (SiC) from SiCED, to use as the active switch component in a high-temperature operation DC/DC-boost converter, has been investigated. The switching loss for room temperature (RT) and on-state resistance (Ron) for RT up to 170°C is investigated. Since the SiC VJFET has a buried body diode it is also ideal to use instead of a switch and diode setup. The voltage drop over the body diode decreases slightly with a higher temperature. A short-circuit test has also been conducted, which shows a high ruggedness.


Author(s):  
Ratil H Ashique ◽  
Zainal Salam

This paper presents a comparative analysis of the ZVZCS soft switching technique with the ZVS and the ZCS counterpart. The generalization of the voltage-current crossover or the energy loss factor obtained from simulation of the prototype converter shows that the ZVZCS significantly reduces the loss and helps to improve the efficiency of the converter as compared to the ZVS or the ZCS. On the other hand, it is also found that the soft switching range of operation of the ZVS and the ZCS are largely affected by the maximum switch voltage and switch current respectively. In contrary, these factors have a negligible effect on the ZVZCS operation which results in an extended range of soft switching operation. Additionally, a detailed LTPICE simulation is performed for selected ZVS, ZCS and ZVSCS topologies from the recent literature and the switching losses in the main switches of the converters are measured. It is observed that the energy losses in the ZVZCS mode are reduced on average by approximately 26 % at turn on and 20 % at the turn off as compared to the ZVS and the ZCS. Besides, the low standard deviation in this mode confirms a stable low loss profile which renders extended soft switching range. An experimental test is also conducted by building the prototype converter to verify the simulation results. It is found that the switching losses are minimum while the converter is operated in the ZVZCS mode. Besides, the efficiency drop remains consistently low as compared to the ZVS and the ZCS in the whole operating range. Resultantly, the simulation and the experimental results are both found to be consistent.


Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2619
Author(s):  
Jongwoon Yoon ◽  
Kwangsoo Kim

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).


2019 ◽  
Vol 36 (3) ◽  
pp. 90-94
Author(s):  
Barbara Swatowska ◽  
Piotr Panek ◽  
Dagmara Michoń ◽  
Aleksandra Drygała

Purpose The purpose of this study was the comparison and analysis of the electrical parameters of two kinds of silicon solar cells (mono- and multicrystalline) of different emitter resistance. Design/methodology/approach By controlling of diffusion parameters, silicon mono- (Cz-Si) and multicrystalline (mc-Si) solar cells with different emitter resistance values were produced – 22 and 48 Ω/□. On the basis of current-voltage measurements of cells and contact resistance mapping, the properties of final solar cells based on two different materials were compared. Additionally, the influence of temperature on PV cells efficiency and open circuit voltage (Uoc) were investigated. The PC1D simulation was useful to determine spectral dependence of external quantum efficiency of solar cells with different emitter resistance. The silicon solar cells of 25 cm2 area and 240 µm thickness were investigated. Findings Considering the all stages of cell technology, the best structure is silicon solar cell with sheet resistance (Rsheet) of 45-48 Ω/□. Producing of an emitter with this resistance allowed to obtain cells with a fill factor between 0.725 and 0.758, Uoc between 585 and 612 mV, short circuit current (Isc) between 724 and 820 mA. Originality/value Measurements and analysis confirmed that mono- and multicrystalline silicon solar cells with 48 Ω/□ emitter resistance have better parameters than cells with Rsheet of 22 Ω/□. The contact resistance is the highest for mc-Si with Rsheet of 48 Ω/□ and reaches the value 3.8 Ωcm.


2020 ◽  
Vol 1004 ◽  
pp. 783-788
Author(s):  
Ki Jeong Han ◽  
Ajit Kanale ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The electrical characteristics of the 1.2-kV rated 4H-SiC accumulation-channel split-gate octagonal cell MOSFET (SG-OCTFET) are experimentally compared with linear, square, hexagonal, octagonal, and compact-octagonal cell topologies. The specific on-resistance of the SG-OCTFET is 52% larger than the conventional linear cell topology. However, the SG-OCTFET has: (i) high-frequency figure-of-merit HFFOM[Ron×Cgd] 9.4×, 6.1×, 2.6×, 2.0×, and 1.8× superior to the square, hex, linear, octagonal, and compact-octagonal cells; (ii) fastest switching performance among all cell topologies, with 26% smaller switching energy loss than the conventional linear cell topology; and (iii) short circuit capability 1.5× longer than the conventional linear cell topology. The SG-OCTFET device is therefore an optimum candidate for high frequency applications of SiC MOSFETs.


2020 ◽  
Vol 67 (9) ◽  
pp. 3685-3690
Author(s):  
Tongtong Yang ◽  
Yan Wang ◽  
Ruifeng Yue
Keyword(s):  

2015 ◽  
Vol 62 (9) ◽  
pp. 2952-2958 ◽  
Author(s):  
Carmine Abbate ◽  
Giovanni Busatto ◽  
Annunziata Sanseverino ◽  
Francesco Velardi ◽  
Cesare Ronsisvalle

2010 ◽  
Vol 645-648 ◽  
pp. 933-936 ◽  
Author(s):  
Rudolf Elpelt ◽  
Peter Friedrichs ◽  
Jürgen Biela

Since SiC VJFETs are believed to offer extremely fast turn on and turn off processes it is important to understand how these transients are tailored by the layout. Regarding the basic layouts two main topologies are under investigation today – structures with the well known SIT layout with purely vertical current flow and lateral vertical concepts where the current flow through the channel is in lateral direction and the vertical current flow takes place in the drift region only. In this paper we will focus on differences in the electric characteristics of both structures and the relation of the dynamic behavior to the topology and the layout of the switches. For the analysis, 1200V VJFETs based on the two basic topologies were manufactured having approximately the same total and active device area. It turns out that the SIT switches under investigation suffer from a high internal gate resistance in the p-doped layers and a relatively high gate drain capacitance.


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