scholarly journals Simulation Studies of a Trench MOS Device Structure with Small Figures of Merit

2018 ◽  
Vol 208 ◽  
pp. 03005
Author(s):  
Junhong Li
Keyword(s):  
Drift Region ◽  
Charge Balance ◽  
Device Structure ◽  
High Permittivity ◽  
Voltage Range ◽  
Charge Imbalance ◽  
Figures Of Merit ◽  
Simulation Results ◽  
Mos Device ◽  
Gate Charge

We proposed a vertical high permittivity trench power MOS (HKTMOS) device with alternating N&P drift region and high permittivity (HK) trench sandwiched in between. The unique structure guarantees uniform potential distribution for wide voltage range at block state owing to both HK potential modulation effect and superjunction (SJ) charge balance. The specific on-resistance (Rons) of HKTMOS is in orders of magnitude lower than the SJ counterparts at the on state because of the strong accumulation effect brought by HK trench. Although the gate charge also significantly rises because of the accumulation, the figures of merit (FOM) of HKTMOS still reduces considerably than the SJ under same BV. An expression for FOM is derived demonstrating that the FOM of HKTMOS is proportional to the square of HK trench depth, which agrees on with simulation results well. The simulation results indicate that within the BV range of 500~2000V, the Rons and FOM of HKTMOS are in 1~2 orders of magnitude lower and 17.4%~44.1% of SJ, respectively under the same BV condition. Furthermore, HKTMOS also demonstrates better charge imbalance tolerance than SJ.

Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance

2018 ◽  
Vol 924 ◽  
pp. 563-567
Author(s):  
Md Monzurul Alam ◽  
Dallas T. Morisette ◽  
James A. Cooper
Keyword(s):  
Drift Region ◽  
Charge Balance ◽  
Ideal Case ◽  
Charge Imbalance ◽  
Blocking Voltage ◽  
Practical Design ◽  
Proper Design ◽  
Improved Performance ◽  
The Relationship ◽  
The Ideal

In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance Ron,sp and blocking voltage VBR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

scholarly journals An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device

2018 ◽  
Vol 201 ◽  
pp. 02003
Author(s):  
Shao Ming Yangi ◽  
Gene Sheu ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
Tzu Chieh Lee ◽  
...  
Keyword(s):  
Lower Energy ◽  
3D Structure ◽  
Doping Profile ◽  
Drift Region ◽  
Charge Balance ◽  
Device Structure ◽  
High Side ◽  
Oxide Ratio ◽  
Buried Layer ◽  
P Type

We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to silicon-di-oxide ratio with side trench. The high-side can also be developed by placing an NBL structure which can deliver a high as over 200V isolation voltage. The 3D structure can clear see the optimized linear p-top and n-drift region have better charge balance with linear doping profile to get the benchmark breakdown voltage (BVdss) of 80V with on-resistance (Ron) as low as 130 mΩ-mm2 and 100V with on-resistance as low as 175 mΩ-mm2.The linear p-type buried layer using high dosage and lower energy to achieve the better SOA and higher isolation voltage. Optimized linear p-top and PBL can improve Ron by 32.5% compare to other 100V high side device which have done from reference.

Design Technique of High Power Efficiency LLC DC-DC Converters for Photovoltaic Cells

2018 ◽  
Vol 2 (1) ◽  
pp. 30
Author(s):  
Hisatsugu Kato ◽  
Yoichi Ishizuka ◽  
Kohei Ueda ◽  
Shotaro Karasuyama ◽  
Atsushi Ogasahara
Keyword(s):  
High Power ◽  
Power Efficiency ◽  
Photovoltaic Cells ◽  
Input Voltage ◽  
Design Technique ◽  
Load Range ◽  
Voltage Range ◽  
Simulation Results ◽  
Secondary Side ◽  
High Power Efficiency

This paper proposes a design technique of high power efficiency LLC DC-DC Converters for Photovoltaic Cells. The secondary side circuit and transformer fabrication of proposed circuit are optimized for overcoming the disadvantage of limited input voltage range and, realizing high power efficiency over a wide load range of LLC DC-DC converters. The optimized technique is described with theoretically and with simulation results. Some experimental results have been obtained with the prototype circuit designed for the 80 - 400 V input voltage range. The maximum power efficiency is 98 %.

scholarly journals Efficiency Enhancement of Flexible Mode Bridgeless Boost Rectifier

2019 ◽  
Vol 9 (2) ◽  
pp. 1503-1508
Keyword(s):  
Power System ◽  
Input Voltage ◽  
Efficiency Enhancement ◽  
Fast Recovery ◽  
High Input ◽  
Voltage Range ◽  
Low Input ◽  
Flexible Mode ◽  
Simulation Results ◽  
Boost Rectifier

Most of the devices in power system become faulty due to the large content of harmonics present in voltage and current. It is mainly caused by the conduction losses in the system. At first, it is necessary to determine the extent of harmonic present by calculating the total harmonic distortions i.e., root over sum of the integral harmonics divide by fundamental harmonic. Later, identification of type of method for reducing harmonics is essential. In this project we are mainly focusing on two types of PFC bridge boost rectifier to improve the efficiency for low and high input voltage range. It using back to back bridgeless PFC boost rectifier for high input voltage and for low input voltage range, three level bridgeless boost rectifiers respectively. Fast recovery diode instead of normal diodes for better reliability and efficiency is utilized. The end model is obtained by combining two circuits BTBBL (Back to back bridgeless boost PFC) and TLBL (Three level bridgeless boost PFC) to get the FMBL (Flexible mode bridgeless boost PFC). Due to presence of less no of components, conduction losses are less hence less distortion is observed with improved efficiency. A simulation is carried out for all three models using MATLAB Simulink platform. In hardware, TLP250 driver for MOSFET is used and which is interfaced with PIC microcontroller. The hardware results are obtained that validates the simulation results.

Impact of Device Structure on Neutron-Induced Single-Event Effect in SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 738-741
Author(s):  
Hiroshi Kono ◽  
Teruyuki Ohashi ◽  
Takao Noda ◽  
Kenya Sano
Keyword(s):  
Threshold Voltage ◽  
Drift Region ◽  
Single Event ◽  
Drain Voltage ◽  
Device Structure ◽  
Pin Diodes ◽  
Power Mosfets ◽  
Single Event Effect ◽  
Significant Difference ◽  
Avalanche Breakdown Voltage

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.

New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)

2013 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
Abderrezak Marzaki ◽  
V. Bidal ◽  
R. Laffont ◽  
W. Rahajandraibe ◽  
J-M. Portal ◽  
...  
Keyword(s):  
Low Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Floating Gate ◽  
Dual Control ◽  
Switching Voltage ◽  
Voltage Range ◽  
Rail To Rail ◽  
Floating Gate Transistor ◽  
Simulation Results

This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages <em>V<sub>TH- </sub></em>(low switching voltage) and <em>V<sub>TH+ </sub></em>(high switching voltage).

scholarly journals Hybrid Dielectric Resonator Antenna Composed of High-Permittivity Dielectric Resonator for Wireless Communications in WLAN and WiMAX

2012 ◽  
Vol 2012 ◽  
pp. 1-6 ◽  
Author(s):  
Yih-Chien Chen
Keyword(s):  
Wireless Communications ◽  
Dielectric Resonator ◽  
Simulation Software ◽  
Dielectric Resonator Antenna ◽  
High Permittivity ◽  
Resonant Frequencies ◽  
Rectangular Slot ◽  
Measurement Results ◽  
Simulation Results ◽  
Good Agreement

The-hybrid dielectric resonator antenna consisted of a cylindrical high-permittivity dielectric resonator, a rectangular slot, and two-rectangular patches were implemented. The hybrid dielectric resonator antenna had three resonant frequencies. The lower, middle, and higher resonant frequencies were associated with the rectangular slot, rectangular patches, and dielectric resonator, respectively. Parametric investigation was carried out using simulation software. The proposed hybrid dielectric resonator antenna had good agreement between the simulation results and the measurement results. The hybrid dielectric resonator antenna was implemented successfully for application in 2.4/5.2/5.8 GHz of WLAN and 2.5/3.5/5.5 GHz of WiMAX simultaneously.

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