scholarly journals An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device

2018 ◽  
Vol 201 ◽  
pp. 02003
Author(s):  
Shao Ming Yangi ◽  
Gene Sheu ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
Tzu Chieh Lee ◽  
...  
Keyword(s):  
Lower Energy ◽  
3D Structure ◽  
Doping Profile ◽  
Drift Region ◽  
Charge Balance ◽  
Device Structure ◽  
High Side ◽  
Oxide Ratio ◽  
Buried Layer ◽  
P Type

We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to silicon-di-oxide ratio with side trench. The high-side can also be developed by placing an NBL structure which can deliver a high as over 200V isolation voltage. The 3D structure can clear see the optimized linear p-top and n-drift region have better charge balance with linear doping profile to get the benchmark breakdown voltage (BVdss) of 80V with on-resistance (Ron) as low as 130 mΩ-mm2 and 100V with on-resistance as low as 175 mΩ-mm2.The linear p-type buried layer using high dosage and lower energy to achieve the better SOA and higher isolation voltage. Optimized linear p-top and PBL can improve Ron by 32.5% compare to other 100V high side device which have done from reference.

A new partial SOI power device structure with P-type buried layer

2005 ◽  
Vol 49 (12) ◽  
pp. 1965-1968 ◽  
Author(s):  
Baoxing Duan ◽  
Bo Zhang ◽  
Zhaoji Li
Keyword(s):  
Power Device ◽  
Device Structure ◽  
Buried Layer ◽  
P Type

scholarly journals Simulation Studies of a Trench MOS Device Structure with Small Figures of Merit

2018 ◽  
Vol 208 ◽  
pp. 03005
Author(s):  
Junhong Li
Keyword(s):  
Drift Region ◽  
Charge Balance ◽  
Device Structure ◽  
High Permittivity ◽  
Voltage Range ◽  
Charge Imbalance ◽  
Figures Of Merit ◽  
Simulation Results ◽  
Mos Device ◽  
Gate Charge

We proposed a vertical high permittivity trench power MOS (HKTMOS) device with alternating N&P drift region and high permittivity (HK) trench sandwiched in between. The unique structure guarantees uniform potential distribution for wide voltage range at block state owing to both HK potential modulation effect and superjunction (SJ) charge balance. The specific on-resistance (Rons) of HKTMOS is in orders of magnitude lower than the SJ counterparts at the on state because of the strong accumulation effect brought by HK trench. Although the gate charge also significantly rises because of the accumulation, the figures of merit (FOM) of HKTMOS still reduces considerably than the SJ under same BV. An expression for FOM is derived demonstrating that the FOM of HKTMOS is proportional to the square of HK trench depth, which agrees on with simulation results well. The simulation results indicate that within the BV range of 500~2000V, the Rons and FOM of HKTMOS are in 1~2 orders of magnitude lower and 17.4%~44.1% of SJ, respectively under the same BV condition. Furthermore, HKTMOS also demonstrates better charge imbalance tolerance than SJ.

Adsorption of Carbon Monoxide on Pd/SiO2/Si(111) Studied by Core-Level Photoemission

1998 ◽  
Vol 63 (11) ◽  
pp. 1793-1802 ◽  
Author(s):  
Zdeněk Bastl ◽  
Tomáš Šarapatka
Keyword(s):  
Carbon Monoxide ◽  
Photoelectron Spectroscopy ◽  
Co Adsorption ◽  
Charge Balance ◽  
Adsorption Activity ◽  
Chemical States ◽  
Adsorbed Co ◽  
Pd Clusters ◽  
Almost All ◽  
P Type

X-Ray photoelectron spectroscopy (XPS) has been used to study the adsorption of carbon monoxide on Pd dispersed on oxidized Si(111) surface. A fraction of the deposited Pd diffusing at room temperature to the SiO2/Si interface increases with decreasing SiO2 thickness. For oxide layers thinner than ≈1 nm, almost all deposited Pd diffuses to SiO2/Si interface forming there Si silicide. Consequently, the amount of adsorbed CO is dependent on the thickness of the thermally grown SiO2 layer. Two different chemical states of adsorbed carbon atoms, the population of which depends on the amount of the Pd deposited, are observed in the C (1s) spectra of adsorbed CO. Adsorption activity of Pd clusters does not depend on whether n- or p-type Si is used. Comparison of the experimental Pd/CO concentration ratios with those calculated assuming several different modes of the Pd growth on SiO2/Si points to the pseudo-Stranski-Krastanow mode (flat clusters with incomplete condensation of the first layer) at 300 K. Changes in charge balance across the Pd/SiO2/Si interface caused by CO adsorption are discussed in terms of the surface photovoltage effect and work function variation.

scholarly journals Large Area Emission in p-Type Polymer-Based Light-Emitting Field-Effect Transistors by Incorporating Charge Injection Interlayers

Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 901
Author(s):  
Gizem Acar ◽  
Muhammad Javaid Iqbal ◽  
Mujeeb Ullah Chaudhry
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Charge Injection ◽  
Limiting Factors ◽  
Hole Injection ◽  
Large Area ◽  
Device Structure ◽  
Light Emitting ◽  
Emission Area ◽  
P Type

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.

12 kV 4H-SiC p-IGBTs with Record Low Specific On-Resistance

2008 ◽  
Vol 600-603 ◽  
pp. 1187-1190 ◽  
Author(s):  
Q. Jon Zhang ◽  
Charlotte Jonas ◽  
Joseph J. Sumakeris ◽  
Anant K. Agarwal ◽  
John W. Palmour
Keyword(s):  
Carrier Lifetime ◽  
Drift Region ◽  
Gate Bias ◽  
Enhancement Layer ◽  
Channel Mobility ◽  
Dc Characteristics ◽  
Blocking Voltage ◽  
High Carrier ◽  
P Type ◽  
First Time

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

Quantum-Confined Optical Interband Transitions in 5-Doped Doping Superlattices

1989 ◽  
Vol 145 ◽  
Author(s):  
E. F. Schubert ◽  
T. D. Harris ◽  
J. E. Cunningham
Keyword(s):  
Emission Spectra ◽  
Doping Profile ◽  
Luminescence Spectra ◽  
Interband Transitions ◽  
Doping Technique ◽  
Quantum Confined ◽  
P Type ◽  
First Time ◽  
Experimental Absorption ◽  
Good Agreement

AbstractOptical absorption and photoluminescence experiments are performed on GaAs doping superlattices, which have a δ-function-like doping profile of alternating n-type and p-type dopant sheets. Absorption and emission spectra reveal for the first time the clear signature of quantum-confined interband transitions. The peaks of the experimental absorption and luminescence spectra are assigned to calculated energies of quantum-confined transitions with very good agreement. It is shown that the employment of the δ-doping technique results in improved optical properties of doping superlattices.

Impact of Device Structure on Neutron-Induced Single-Event Effect in SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 738-741
Author(s):  
Hiroshi Kono ◽  
Teruyuki Ohashi ◽  
Takao Noda ◽  
Kenya Sano
Keyword(s):  
Threshold Voltage ◽  
Drift Region ◽  
Single Event ◽  
Drain Voltage ◽  
Device Structure ◽  
Pin Diodes ◽  
Power Mosfets ◽  
Single Event Effect ◽  
Significant Difference ◽  
Avalanche Breakdown Voltage

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.

Hg1−x−yMnxCdyTe Alloys for 1.3−1.8 μm Photodiode Applications

1986 ◽  
Vol 89 ◽  
Author(s):  
S. H. Shin ◽  
J. G. Pasko ◽  
D. S. Lo ◽  
W. E. Tennant ◽  
J. R. Anderson ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Liquid Phase Epitaxy ◽  
Room Temperature ◽  
Reverse Bias ◽  
Fiber Optic ◽  
Superior Performance ◽  
Device Performance ◽  
Device Structure ◽  
Cdte Substrate ◽  
P Type

AbstractHgMnCdTe/CdTe photodiodes with responsivity cutoffs of up to 1.54 pm have been fabricated by liquid phase epitaxy (LPE). The mesa device structure consists of a boron-implanted mosaic fabricated on a p-type Hg1−x−yMnxCdyTe layer grown on a CdTe substrate. A reverse breakdown voltage (VB) of 50 V and a leakage current density of 1.5 × 10−4 A/cm2 at V = −10 V was measured at room temperature (295K). A 0.75 pF capacitance was also measured under a 5 V reverse bias at room temperature. This device performance based on the quaternary HgMnCdTe shows both theoretical and practical promise of superior performance for wavelengths in the range 1.3 to 1.8 μm for fiber optic applications.

Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance

2018 ◽  
Vol 924 ◽  
pp. 563-567
Author(s):  
Md Monzurul Alam ◽  
Dallas T. Morisette ◽  
James A. Cooper
Keyword(s):  
Drift Region ◽  
Charge Balance ◽  
Ideal Case ◽  
Charge Imbalance ◽  
Blocking Voltage ◽  
Practical Design ◽  
Proper Design ◽  
Improved Performance ◽  
The Relationship ◽  
The Ideal

In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance Ron,sp and blocking voltage VBR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

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