Memristive combinational logic circuits and stochastic computing implementation scheme

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tianshu Li ◽  
Shukai Duan ◽  
Jun Liu ◽  
Lidan Wang
Keyword(s):  
Response Time ◽  
Fault Tolerant ◽  
Computing System ◽  
Oxide Semiconductor ◽  
Cmos Circuits ◽  
Combinational Logic ◽  
Content Type ◽  
Stochastic Computing ◽  
Memristive System ◽  
Implementation Scheme

Purpose Stochastic computing which is an alternative method of the binary calculation has key merits such as fault-tolerant capability and low hardware cost. However, the hardware response time of it is required to be very fast due to its bit-wise calculation mode. While the complementary metal oxide semiconductor (CMOS) components are difficult to meet the requirements aforementioned. For this, the stochastic computing implementation scheme based on the memristive system is proposed to reduce the response time. The purpose of this paper is to provide the implementation scheme based memristive system for the stochastic computing. Design/methodology/approach The hardware structure of material logic based on the memristive system is realized according to the advantages of the memristor. After that, the scheme of NOT logic, AND logic and multiplexer are designed, which are the basic units of stochastic computing. Furthermore, a stochastic computing system based on memristive combinational logic is structured and its validity is verified successfully by operating a case. Findings The numbers of the elements of the proposed stochastic computing system are less than the conventional stochastic computing based on CMOS circuits. Originality/value The paper proposed a novel implementation scheme for stochastic computing based on the memristive systems, which are different from the conventional stochastic computing based on CMOS circuits.

Transient analysis of computing system with reboot and recovery delay

2020 ◽  
Vol 37 (6/7) ◽  
pp. 983-1005
Author(s):  
Chandra Shekhar ◽  
Amit Gupta ◽  
Madhu Jain ◽  
Neeraj Kumar
Keyword(s):  
Sensitivity Analysis ◽  
Fault Tolerant ◽  
Transient State ◽  
Recovery Process ◽  
Computing System ◽  
Time To Failure ◽  
Mean Time To Failure ◽  
Content Type ◽  
Imperfect Coverage ◽  
Mean Time

PurposeThe purpose of this paper is to present a sensitivity analysis of fault-tolerant redundant repairable computing systems with imperfect coverage, reboot and recovery process.Design/methodology/approachIn this investigation, the authors consider the computing system having a finite number of identical working units functioning simultaneously with the provision of standby units. Working and standby units are prone to random failure in nature and are administered by unreliable software, which is also likely to unpredictable failure. The redundant repairable computing system is modeled as a Markovian machine interference problem with exponentially distributed failure rates and service rates. To excerpt the failed unit from the computing system, the system either opts randomized reboot process or leads to recovery delay.FindingsTransient-state probabilities have been determined with which the authors develop various reliability measures, namely reliability/availability, mean time to failure, failure frequency, and so on, and queueing characteristics, namely expected number of failed units, the throughput of the system and so on, for the predictive purpose. To spectacle the practicability of the developed model, a numerical simulation, sensitivity analysis and so on for different parameters have also been done, and the results are summarized in the tables and graphs. The transient results are helpful to analyze the developing model of the system before having the stability of the system. The derived measures give direct insights into parametric decision-making.Social implicationsThe conclusion has been drawn, and future scope is remarked. The present research study would help system analyst and system designer to make a better choice/decision in order to have the economical design and strategy based on the desired mean time to failure, reliability/availability of the systems and other queueing characteristics.Originality/valueDifferent from previous investigations, this studied model provides a more accurate assessment of the computing system compared to uncertain environments based on sensitivity analysis.

A fault-tolerant design for a digital comparator based on nano-scale quantum-dotcellular automata

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Wenhua Huang ◽  
Juan Ren ◽  
Jinglong Jiang ◽  
J. Cheng
Keyword(s):  
Single Cell ◽  
Performance Metrics ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Logical Function ◽  
Switching Speed ◽  
Content Type ◽  
Nano Scale ◽  
Digital Comparator

Purpose Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA. Design/methodology/approach As the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator. Findings Four elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects. Originality/value A novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.

Integration of fault-tolerant feature to OMIEEPB routing protocol in wireless sensor network

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
I. Nasurulla ◽  
R. Kaniezhil
Keyword(s):  
Wireless Sensor Network ◽  
Response Time ◽  
Sensor Network ◽  
Routing Protocol ◽  
Fault Tolerant ◽  
Data Communication ◽  
Operation Time ◽  
Wireless Sensor ◽  
Signal Interference ◽  
Content Type

PurposeWhereas a human operator is hard to observe the networking infrastructure and its functions on a continuous basis, wireless sensor network (WSN) nodes must overcome faults and route the perceived data to the sink/base stations (BS). The main target of this research article is to ensure the fault-tolerance (FT) capability, especially for transmission of sensed data to its destination without failure. Thus, through this paper, a fuzzy-based subordinate support (FSS) system is introduced as an additional feature to the existing optimized mobile sink improved energy efficient Power-Efficient Gathering in Sensor Information Systems (PEGASIS)-based (OMIEEPB) routing protocol, which lacks focus on ensuring the FT capabilities to the selected leaders of the corresponding chain. The central focus of FSS is to prevent the incident of fault, especially to the cluster heads.Design/methodology/approachWSNs encounter several issues owing to random events or different causes such as energy exhaustion, negative influences of the deployed region, signal interference, unbalanced supply routes, instability of motes due to misalignments and collision, which ultimately intends the failure of the network. Throughout the past investigation periods, researchers gain an understanding of fault-tolerant strategies that may improve the data integrity or reliability, precision, energy efficiency, the life expectancy of the system and reduce/prevent the failure of deployed components. If that is the case, the maximum chances of data packets (sensed) needed to be transferred reliably and accurately to the sink node or BS are degraded.FindingsThe FSS system utilizes the fuzzy logic concepts that have been proved to be beneficial since it permits several parameters to be combined effectively and evaluated. Here, near-point, residual energy, total operation time and past average processing time are considered as vital parameters. Moreover, the FSS system ensures the key performance activities of the network, such as optimization of response time, enhancing the data transmission reliability and accuracy. Simulation-based experiments are carried out through the Mannasim framework. After several experimental executions, the outcome of the proposed system is analyzed through elaborated comparison with the advanced existing systems.Originality/valueFinally, it has been observed that the FSS system not only enhanced the FT features to OMIEEPB but also assures the improved accuracy level (>95%) with optimized response time (<0.09 s) during data communication between leaders and the normal nodes.

Research on robust adaptive sliding film fault-tolerant control under nonlinear distortion of signal transmission in amorphous flat air-to-ground wireless ad-hoc network system

2022 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Zhifang Wang ◽  
Jianguo Yu ◽  
Shangjing Lin
Keyword(s):  
Nonlinear Distortion ◽  
Ad Hoc ◽  
Fault Tolerant ◽  
Signal Transmission ◽  
Network System ◽  
Long Distance ◽  
Content Type ◽  
Wireless Signal ◽  
Robust Adaptive ◽  
Self Organizing

Purpose To solve the above problems and ensure the stability of the ad hoc network node topology in the process of wireless signal transmission, this paper aims to design a robust adaptive sliding film fault-tolerant controller under the nonlinear distortion of signal transmission in an amorphous flat air-to-ground wireless ad hoc network system. Design/methodology/approach This paper designs a robust adaptive sliding film fault-tolerant controller under the nonlinear distortion of signal transmission in an amorphous flat air-to-ground wireless ad hoc network system. Findings The simulation results show that the amorphous flat wireless self-organizing network system has good nonlinear distortion fault-tolerant correction ability under the feedback control of the designed controller, and the system has the asymptotically stable convergence ability; the test results show: the node topology of the self-organizing network structural stability is significantly improved, which provides a foundation for the subsequent realization of long-distance transmission of ad hoc network nodes. Research limitations/implications Because of the chosen research approach, the research results may lack generalizability. Therefore, researchers are encouraged to test the proposed propositions further. Originality/value The controller can extract the fault information caused by nonlinear distortion in the wireless signal transmission process, and at the same time, its feedback matrix K can gradually converge the generated wireless signal error to zero, to realize the stable transmission of the wireless signal.

scholarly journals Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 851 ◽  
Author(s):  
Gil-Tomàs ◽  
Gracia-Morán ◽  
Saiz-Adalid ◽  
Gil-Vicente
Keyword(s):  
Field Effect Transistor ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Graphene Nanoribbon ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fault Models ◽  
New Materials ◽  
Effect Transistor

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

Process voltage temperature analysis of MOS based balanced pseudo-resistors for biomedical analog circuit applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kulbhushan Sharma ◽  
Anisha Pathania ◽  
Jaya Madan ◽  
Rahul Pandey ◽  
Rajnish Sharma
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Common Mode ◽  
Temperature Variations ◽  
Time Constants ◽  
Content Type ◽  
Common Mode Voltage ◽  
Design Techniques

Purpose Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications. Design/methodology/approach In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process. Findings The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations. Research limitations/implications Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits. Social implications The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics. Originality/value The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Distributed robust H∞ adaptive fault-tolerant control of amorphous and flat air-to-ground wireless self-organizing network system

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Zhifang Wang ◽  
Jianguo Yu ◽  
Shangjing Lin ◽  
Junguo Dong ◽  
Zheng Yu
Keyword(s):  
Flight Control ◽  
Control Algorithm ◽  
Ad Hoc ◽  
Fault Tolerant ◽  
Fault Tolerant Control ◽  
Integrated System ◽  
External Disturbances ◽  
Content Type ◽  
Actuator Failures ◽  
Wireless Signal

Purpose The paper takes the air-ground integrated wireless ad hoc network-integrated system as the research object, this paper aims to propose a distributed robust H∞ adaptive fault-tolerant control algorithm suitable for the system to distribute to solve the problem of control and communication failure at the same time. Design/methodology/approach In the paper, the authors propose a distributed robust H∞ adaptive fault-tolerant control algorithm suitable for the air-ground integrated wireless ad hoc network-integrated system. Findings The results show that the integrated system has good robustness and fault tolerance performance indicators for flight control and wireless signal transmission when confronted with external disturbances, internal actuator failures and wireless network associated failures and the flight control curve of the quadrotor unmanned aerial vehicle (UAV) is generally smooth and stable, even if it encounters external disturbances and actuator failures, its fault tolerance performance is very good. Then in the range of 400–800 m wireless communication distance, the success rate of wireless signal loop transmission is stable at 80%–100% and the performance is at least relatively improved by 158.823%. Originality/value This paper takes the air-ground integrated wireless ad hoc network-integrated system as the research object, based on the robust fault-tolerant control algorithm, the authors propose a distributed robust H∞ adaptive fault-tolerant control algorithm suitable for the system and through the Riccati equation and linear matrix inequation method, the designed distributed robust H∞ adaptive fault-tolerant controller further optimizes the fault suppression factor γ, so as to break through the limitation of only one Lyapunov matrix for different fault modes to distribute to solve the problem of control and communication failure at the same time.

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Francisco Javier Plascencia Jauregui ◽  
Agustín Santiago Medina Vazquez ◽  
Edwin Christian Becerra Alvarez ◽  
José Manuel Arce Zavala ◽  
Sandra Fabiola Flores Ruiz
Keyword(s):  
Metal Oxide ◽  
Charge Density ◽  
Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Poisson’S Equation ◽  
Oxide Semiconductor ◽  
Volume Charge ◽  
Poisson's Equation ◽  
Content Type ◽  
Volume Charge Density

Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

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