Studies on the Thermal Cycling Reliability of Fine Pitch Cu/SnAg Double-Bump Flip Chip Assemblies on Organic Substrates: Experimental Results and Numerical Analysis

2008 ◽  
Author(s):  
Ho-Young Son ◽  
Kyung-Wook Paik ◽  
Ilho Kim ◽  
Jin-Hyoung Park ◽  
Soon-Bok Lee ◽  
...  
Keyword(s):  
Numerical Analysis ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Experimental Results ◽  
Organic Substrates ◽  
Fine Pitch

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Thermal Cycling Reliability and Delamination of Anisotropic Conductive Adhesives Flip Chip on Organic Substrates With Emphasis on the Thermal Deformation

2005 ◽  
Vol 127 (2) ◽  
pp. 86-90 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Myung-Jin Yim ◽  
Kyung-Wook Paik ◽  
Suk-Jin Ham ◽  
Soon-Bok Lee
Keyword(s):  
Thermal Cycling ◽  
Thermal Deformation ◽  
Flip Chip ◽  
High Sensitivity ◽  
Moiré Interferometry ◽  
Acoustic Microscopy ◽  
Moire Interferometry ◽  
Organic Substrates ◽  
Conductive Adhesives ◽  
Reliability Performance

One of the most important issues whether anisotropic conductive film (ACF) interconnection technology is suitable to be used for flip chip on organic board applications is thermal cycling reliability. In this study, thermally induced deformations and warpages of ACF flip chip assemblies as a function of distance from neutral point (DNP) and ACF materials properties were investigated using in situ high sensitivity moire´ interferometry. For a nondestructive failure analysis, scanning acoustic microscopy investigation was performed for tested assemblies. To elucidate the effects of ACF material properties and DNP on the thermal cycling reliability of ACF assembly, Weibull analysis for the lifetime estimation of ACF joint was performed, and compared with thermal deformations of ACF flip chip assembly investigated by moire´ interferometry. Results indicate that the properties of ACF have a significant role in the thermal deformation and reliability performance during thermal cycling testing. Therefore, optimized ACF properties can enhance ACF package reliability during thermal cycling regime.

Flip Chip Joining with Quaternary Low Melting Temperature Solder Bump Fabricated with Injection Molded Solder

2019 ◽  
Vol 2019 (1) ◽  
pp. 000103-000109 ◽  
Author(s):  
Takashi Hisada ◽  
Toyohiro Aoki ◽  
Eiji Nakamura ◽  
Sayuri Kohara ◽  
Hiroyuki Mori
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Solder Joints ◽  
Quaternary Alloy ◽  
Thermal Cycling Test ◽  
Sac305 Solder ◽  
Cycling Test ◽  
Fine Pitch ◽  
Alloy Solder ◽  
Injection Molded

Abstract IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.

Fatigue Testing of Copper Nanoparticle Based Joints and Bonds

2021 ◽  
Author(s):  
Rajesh Sivasubramony ◽  
Maan Z. Kokash ◽  
Sanoop Thekkut ◽  
Ninand Shahane ◽  
Patrick Thompson ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Maximum Temperature ◽  
Nano Particle ◽  
Test Results ◽  
Fine Pitch ◽  
Effects Of Aging ◽  
Sintered Ag

Abstract Fused or sintered Cu nanoparticle structures are potential alternatives to solder for ultra-fine pitch flip chip assembly and to sintered Ag for heat sink attach in high temperature microelectronics. Meaningful testing and interpretation of test results in terms of what to expect under realistic use conditions do, however, require a mechanistic picture of degradation and damage mechanisms. As far as fatigue goes, such a picture is starting to emerge. The porosity of sintered nano-particle structures significantly affects their behavior in cycling. The very different sensitivities to parameters, compared to solder, means new protocols will be required for the assessment of reliability. The present study focused on fatigue in both isothermal and thermal cycling. During the latter, all damage occurs at the low temperature extreme, so life is particularly sensitive to the minimum temperature and any dwell there. Variations in the maximum temperature up to 125 °C did not affect, but a maximum temperature of 200 °C led to much faster damage. Depending on particle size and sintering conditions deformation and damage properties may also degrade rapidly over time. Our picture allows for recommendations as to more relevant test protocols for vibration, thermal cycling, and combinations of these, including effects of aging, as well as for generalization of test results and comparisons in terms of anticipated behavior under realistic long-term use conditions. Also, the fatigue life seems to vary with the ultimate strength, meaning that simple strength testing becomes a convenient reference in materials and process optimization.

Inducing Frictional Force to Enhance the Transient Response in Beams

2019 ◽  
Vol 22 (2) ◽  
pp. 88-93
Author(s):  
Hamed Khanger Mina ◽  
Waleed K. Al-Ashtrai
Keyword(s):  
Numerical Analysis ◽  
Transient Response ◽  
Frictional Force ◽  
Damping Ratio ◽  
Experimental Results ◽  
Damping Capacity ◽  
Tightening Force ◽  
Contact Areas ◽  
Good Agreement ◽  
Ansys Workbench

This paper studies the effect of contact areas on the transient response of mechanical structures. Precisely, it investigates replacing the ordinary beam of a structure by two beams of half the thickness, which are joined by bolts. The response of these beams is controlled by adjusting the tightening of the connecting bolts and hence changing the magnitude of the induced frictional force between the two beams which affect the beams damping capacity. A cantilever of two beams joined together by bolts has been investigated numerically and experimentally. The numerical analysis was performed using ANSYS-Workbench version 17.2. A good agreement between the numerical and experimental results has been obtained. In general, results showed that the two beams vibrate independently when the bolts were loosed and the structure stiffness is about 20 N/m and the damping ratio is about 0.008. With increasing the bolts tightening, the stiffness and the damping ratio of the structure were also increased till they reach their maximum values when the tightening force equals to 8330 N, where the structure now has stiffness equals to 88 N/m and the damping ratio is about 0.062. Beyond this force value, increasing the bolts tightening has no effect on stiffness of the structure while the damping ratio is decreased until it returned to 0.008 when the bolts tightening becomes immense and the beams behave as one beam of double thickness.

Advanced Fault Isolation Technique Using Electro-Optical Terahertz Pulse Reflectometry (EOTPR) for 2D and 2.5D Flip-Chip Package

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Meng Yeow Tay ◽  
Wen Qiu ◽  
J. Alton ◽  
...  
Keyword(s):  
Time Domain ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Experimental Results ◽  
Terahertz Pulse ◽  
Isolation And Identification ◽  
Isolation Technique ◽  
Non Destructive

Abstract Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

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