Abstract
In the high power module applications, the power increasing and the size shrinking becomes one of the major topics for the power module design. Due to both the power increasing and the size decreasing, the power density of the device will be much increased. Therefore, not only the thermal conductivity and stability of the substrate material but the long-term material reliability of the substrate have to be seriously considered. For these reasons, the ceramic PCB becomes one of the best solutions. The ceramic substrates now used are normally based on Ag-printed or direct bonding copper (DBC) technology.
In the case of the Ag-printed ceramic substrate, the pattern resolution and metallization thickness are limited by the Ag-printed process. Also the combination strength of the silver and ceramic substrate by glass (which is normally mixed in the silver paste) is normally not good enough. A thermal dissipation barrier will then be formed between silver and ceramic substrate due to the poor thermal conductivity of the glass material. For the DBC ceramic substrate, DBC substrates are manufactured at 1065°C by the diffusion between ceramic and Cu/CuO layer. A thicker Cu layer thickness of normally more than 300 um is required in the thermal compressing bonding process. The Cu pattern resolution will then be limited by the thickness of the Cu layer. However, the about 5~10% of the voids exist randomly between ceramic and Cu layer is the other major issue.
The resolution issues of the Ag-printed and DBC ceramic substrates make the limitation for the device density design (fine line/width and flip-chip device design become very difficult). The glass material in the Ag printed ceramic substrate and the 5~10% voids existence in DBC ceramic substrate may cause the reliability issue operating at a high power density applications.
For high power density module applications, we introduce the DPC technology on the ceramic substrate. In DPC ceramic substrate system, the sputtered Ti is used as the combination material between Cu and ceramic substrate. And the first copper is then sputtered on the top of Ti layer as seed-layer for the following Cu electrode plating (second cupper layer). By the material and the sputtering process control, several ceramic substrate raw materials can be used, such as Al2O3, AlN, BeO, Si3N4 and so on. The Ti combined/buffer layer provides good adhesion strength and material stability. The second copper layer is plated by electrode casting plating to 3 to 5 oz. (100~150um) in thickness. The key technology of the metal trace plating is the material control of the sputter layers and the second copper layer stress release during plating.
In the DPC system, the double layers design is available. The laser drilled via holes on the various ceramic substrates is introduced. The conducting of the front and back side is connected by the following plating process. The key technology of this process is the stability of the via-holes. We have to make sure the via-holes cleaning, impurity removing and material stability during high temperature laser drilled is well controlled.
DPC ceramic substrates provide a better metal/ceramic interface uniformity and material reliability due to the stable Ti combination material and much less voids in the metal/ceramic interface. Also, the DPC ceramic substrates provide a gold pattern resolution of 50 um line space with tight tolerance of 20 um min. We believe the material characteristic make DPC a very suitable substrate material for high power module applications.
Experimental Study on Inkjet-Printed Passive UHF RFID Tags on Versatile Paper-Based Substrates