Scaling trends of the AES S-box low power consumption in 130 and 65 nm CMOS technology nodes

2009 ◽  
Author(s):  
Dina Kamel ◽  
Francois-Xavier Standaert ◽  
Denis Flandre
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Technology Nodes

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Block Cipher ◽  
Low Power Design ◽  
Cmos Technology ◽  
Smart Cards ◽  
Low Power Consumption

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

scholarly journals Silicon nanomembrane phototransistor flipped with multifunctional sensors toward smart digital dust

2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Flexible Electronics ◽  
Large Scale ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Stimuli Responsive ◽  
Single Chip ◽  
Detection Mechanism ◽  
Silicon Nanomembrane

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.

scholarly journals A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Trong-Tu Bui ◽  
Tadashi Shibata
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Time Domain ◽  
Rank Order ◽  
Cmos Technology ◽  
Floating Gate ◽  
Low Power Consumption ◽  
Associative Memories ◽  
Filtering Function ◽  
Identification Function

We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

A 5-BIT 500-MS/S FLASH ADC USING TIME-DOMAIN COMPARISON

2012 ◽  
Vol 21 (08) ◽  
pp. 1240023 ◽  
Author(s):  
YOUNG-JAE MIN ◽  
HOON-KI KIM ◽  
CHULWOO KIM ◽  
SOO-WON KIM ◽  
GIL-SU KIM
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Time Domain ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Nyquist Frequency ◽  
Flash Adc ◽  
Digital Implementation ◽  
The Time Domain

A 5-bit 500-MS/s time-domain flash ADC is presented. The proposed ADC consists of a reference resistor ladder, two voltage-to-time converter arrays, a time-domain comparator array and a digital encoder without sample-and-hold. In order to achieve low-power consumption with high conversion-speed and to enhance design reusability in terms of a highly digital implementation with more regular mask patterns, the time-domain comparison is devised in the flash ADC. The prototype has been implemented and fabricated in a standard 0.18 μm CMOS technology and occupies 0.132 mm2 without pads. The measured SNDR and SFDR up to the Nyquist frequency are 26.6 dB and 35.1 dB, respectively. And the peak DNL and INL are measured as 0.43 LSB and 0.58 LSB, respectively. The prototype consumes 8 mW with a 1.8-V supply voltage.

scholarly journals Designing ALU using GDI method

2019 ◽  
Vol 8 (3) ◽  
pp. 151
Author(s):  
Mohammadreza Fadaei
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Low Power Consumption ◽  
Ic Design ◽  
Advantages And Disadvantages ◽  
Circuit Resistance

<p>As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.</p>

Design and Implementation of New Feynman and Toffoli (NFT) Gates in Quantum-dot Cellular Automata (QCA)

2017 ◽  
Vol 2 (4) ◽  
pp. 64-67
Author(s):  
Sajjad Waheed ◽  
Md. Golam Rasel
Keyword(s):  
Information Processing ◽  
Power Consumption ◽  
Low Power ◽  
Processing System ◽  
Logic Gates ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Switching Frequency ◽  
Promising Alternative ◽  
Scale Integration

In this paper, New Feynman and Toffoli (NFT) gate is proposed based on QCA logic gates. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. A novel electronics paradigm for information processing and communication by QCA offers technology. QCA technology has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology.

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