scholarly journals POWER REDUCTION TECHNIQUES IN VLSI

2020 ◽  
Vol 5 (2) ◽  
pp. 123-129
Author(s):  
Mehar Sharma ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Abstraction Level ◽  
Reduction Techniques ◽  
Increasing Trend ◽  
Different Types ◽  
The Given

The paper investigates different level of techniques used for power reduction in VLSI. Before,most of the researches were oriented towards bringing about high speed and miniaturization.At present, because of the increasing trend of compact devices, the requirement for low powerconsuming circuits have also increased. This necessitates the need to align the research forreducing power dissipation in VLSI circuits. In the given paper we will briefly discuss aboutthe different types of power reduction techniques at design abstraction level which are adoptedin industries now-a-days. The comparison of traditional techniques and present techniquesare also covered in this paper.

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

Dynamic Measurements of Micro-Meter Particle Detachment on Glass Surfaces

2012 ◽  
Author(s):  
Asmaa Sadek Kassab ◽  
Victor M. Ugaz ◽  
Maria D. King ◽  
Yassin A. Hassan
Keyword(s):  
High Speed ◽  
Single Layer ◽  
Dynamic Measurements ◽  
Complex Motion ◽  
Short Term ◽  
High Speed Imaging ◽  
Increasing Trend ◽  
Different Types ◽  
Glass Surfaces ◽  
Initial Movement

This work presents a high resolution study of the condition under which a transient fluid flow causes spherical glass beads particles of 10–100 μm in size to detach from glass surfaces. The general approach is to conduct well-controlled experiments, to observe individual microparticle motion in short term resuspension, within a period up to 5s, and to focus on the basic detachment mechanisms of the resuspended particles to fully understand and quantify the behavior of particles immediately before liftoff. Particle tracking obtained from high-speed imaging of individual particle with 4000 frames/s, reveal three different types of motion: rolling/bouncing, immediate liftoff (where the particle showed immediate liftoff without any initial rolling/bouncing) and complex motion where particles travel with rolling/bouncing motion on the surface for a certain distance before liftoff. The longer it will take the particle to start its initial movement the more rapid is the liftoff once motion is initiated. The majority of particle trajectories from the glass substrate were parallel to the surface with complex motion, covering 25% of the total distance traveled in rolling/bouncing motion before liftoff. Additionally, Single layer detachment showed that the detachment percentage initially follow an exponentially increasing trend for a period of ∼ 1s, followed by a plateau phase for a period of 5s.

TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

2014 ◽  
Vol 23 (05) ◽  
pp. 1450061 ◽  
Author(s):  
VIJAY KUMAR SHARMA ◽  
MANISHA PATTANAIK
Keyword(s):  
Threshold Voltage ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Deep Submicron ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Leakage Power Dissipation

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

scholarly journals Design of Self Controllable Voltage Level Circuit (SVL) for Low Power and High Speed 12t Sram at 15nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1561-1565
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Dissipation Factor ◽  
Main Concern ◽  
Main Task ◽  
Voltage Level ◽  
Reduction Techniques

Due to trend of decreasing the device Size and increase in the chip density, the complexity in design increased and it became very complex. The main factor which is main concern in this step is Power dissipation. This can be occurring in many forms like Dynamic, subthreshold leakage and Gate leakage. For every situation the designer has to try to reduce this Power Dissipation factor. In this paper we designed a low power 12T SRAM by using the 15nm technology. SRAMs have large number of applications in high speed registers, microprocessors, small memory banks, general computing applications etc. Therefore delay, power, speed, leakage current and stability are the main concerns. These parameters are in trade off to each other. This paper focuses on the leakage current, power and stability in 12T SRAM bit -cell. We introduce a circuit “self - controllable Voltage Level (SVL)” circuit. The main task of this circuit is to reduce the stand-by leakage power of 12T SRAM. In our Work, We are using the Cadence Virtuoso simulation tool for simulating our circuit. After Comparing our results to the previous methods used for reducing the power leakage we found that there is reduction in average power compare to the previous methods used for power reduction techniques.

scholarly journals LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

2013 ◽  
pp. 237-242
Author(s):  
B. DILIP ◽  
P. SURYA PRASAD ◽  
R. S. G. BHAVANI
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Power Reduction ◽  
The Other ◽  
Cmos Circuits ◽  
Reduction Techniques ◽  
Additional Control ◽  
Area Increase ◽  
Leakage Control ◽  
Additional Resistance

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.

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