Fabrication of poly-silicon microwire using conventional photolithography technique: Positive resist mask vs aluminium hard mask

In this work, we demonstrated a method to fabricate and characterize poly-silicon nanowires for biosensing application using conventional photolithography and etching process. Nanowires Mask must be first designed using AutoCAD, before patterning onto chrome mask. Chrome mask was used for better photo masking and to transfer structure onto poly-silicon layer. The poly-silicon nanowires process flow were developed which includes all the fabrication process such as growth, deposition, lithography and etching process. In order to prove the effectiveness of the fabricated devices as a biologically sensor (Biosensor), the poly-silicon nanowires is modified chemically to allow the integration with biological element. The drain (Id) was found to increase after the DNA immobilization and hybridization. These results demonstrate that the in-house fabricated poly-silison nanobiosensor is capable as a platform for label-free biosensing. The morphological characterizations were carried out using a Scanning Electron Microscope (SEM) and Atomic Force Microscope (AFM). Besides that, the electrical measurement of the poly-silicon biosensor were carried out using a KEITHLEY 6487 picoampmeter/voltage source.

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Lithography below 100 nm

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100074367 ◽

1983 ◽

Vol 41 ◽

pp. 96-99

Author(s):

L. D. Jackel

Keyword(s):

Spatial Distribution ◽

Electron Beam ◽

Electron Scattering ◽

Electron Beam Lithography ◽

Substrate Material ◽

Local Electron ◽

Electron Dose ◽

Positive Resist ◽

Exposure Process

Most production electron beam lithography systems can pattern minimum features a few tenths of a micron across. Linewidth in these systems is usually limited by the quality of the exposing beam and by electron scattering in the resist and substrate. By using a smaller spot along with exposure techniques that minimize scattering and its effects, laboratory e-beam lithography systems can now make features hundredths of a micron wide on standard substrate material. This talk will outline sane of these high- resolution e-beam lithography techniques.We first consider parameters of the exposure process that limit resolution in organic resists. For concreteness suppose that we have a “positive” resist in which exposing electrons break bonds in the resist molecules thus increasing the exposed resist's solubility in a developer. Ihe attainable resolution is obviously limited by the overall width of the exposing beam, but the spatial distribution of the beam intensity, the beam “profile” , also contributes to the resolution. Depending on the local electron dose, more or less resist bonds are broken resulting in slower or faster dissolution in the developer.

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Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100131619 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1396-1397

Author(s):

H. Yen ◽

E. P. Kvam ◽

R. Bashir ◽

S. Venkatesan ◽

G. W. Neudeck

Keyword(s):

Integrated Circuits ◽

Polycrystalline Silicon ◽

Silicon Films ◽

Interface Morphology ◽

Oxide Interface ◽

Poly Silicon ◽

Thermal Oxide ◽

Grain Orientations ◽

Polycrystalline Silicon Films ◽

P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

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Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1996p0159 ◽

1996 ◽

Author(s):

E. Widener ◽

S. Tatti ◽

P. Schani ◽

S. Crown ◽

B. Dunnigan ◽

...

Keyword(s):

Failure Analysis ◽

Product Quality ◽

Cmos Process ◽

Designed Experiments ◽

Root Cause ◽

Poly Silicon ◽

New Process ◽

Supply Current ◽

Electrical Analysis ◽

Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

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Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0239 ◽

2013 ◽

Author(s):

Jong Hak Lee ◽

Jong Eun Kim ◽

Chang Su Park ◽

Nam Il Kim ◽

Jang Won Moon ◽

...

Keyword(s):

Leakage Current ◽

Circuit Simulation ◽

The State ◽

Physical Analysis ◽

Cross Sectional ◽

Hard Mask ◽

Current Flows ◽

Voltage Contrast ◽

The One ◽

Zero Voltage

Abstract In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.

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Root Cause Analysis for Pin Leakage

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0217 ◽

2016 ◽

Author(s):

Zhigang Song ◽

Jochonia Nxumalo ◽

Manuel Villalobos ◽

Sweta Pendyala

Keyword(s):

Failure Analysis ◽

Root Cause Analysis ◽

Advanced Technology ◽

Process Step ◽

Cause Analysis ◽

Hard Mask ◽

Technology Node ◽

Root Cause ◽

Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0383 ◽

2012 ◽

Author(s):

Ramachandra Chitakudige ◽

Sarat Kumar Dash ◽

A.M. Khan

Keyword(s):

High Selectivity ◽

Electron Cyclotron Resonance ◽

Random Access ◽

Random Access Memory ◽

Access Memory ◽

Plasma System ◽

Poly Silicon ◽

Hazardous Gases ◽

Wet Etch ◽

Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

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