Optimization of Thermomechanical Reliability of Board-Level Flip-Chip Packages Implemented With Organic or Silicon Substrates

2008 ◽  
Vol 31 (2) ◽  
pp. 174-179 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai
Keyword(s):  
Flip Chip ◽  
Silicon Substrates ◽  
Thermomechanical Reliability ◽  
Board Level

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

2008 ◽  
Vol 85 (4) ◽  
pp. 659-664 ◽  
Author(s):  
Tong Hong Wang ◽  
Ching-Chun Wang ◽  
Yi-Shao Lai ◽  
Kuo-Chin Chang ◽  
Chien-Hsun Lee
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Thermomechanical Reliability ◽  
Board Level

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

2007 ◽  
Vol 30 (1) ◽  
pp. 38-43 ◽  
Author(s):  
Soonwan Chung ◽  
Zhenming Tang ◽  
Seungbae Park
Keyword(s):  
Phase Change ◽  
Flip Chip ◽  
Board Level

Mechanical and Thermal Board Level Reliability Comparison Between Electroless Ni Im. Au and Solder on Pad Surface Finishes for Large Flip Chip BGA Packages

2006 ◽  
Author(s):  
Gnyaneshwar Ramakrishna ◽  
Donghyun Kim ◽  
Mudasir Ahamad ◽  
Lavanya Gopalakrishnan ◽  
Mason Hu ◽  
...  
Keyword(s):  
Surface Finish ◽  
Flip Chip ◽  
High Reliability ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Design Parameters ◽  
Temperature Cycle ◽  
Bga Packages ◽  
Reliability And Robustness ◽  
Board Level

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-a`-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

Low-K Flip Chip Board Level Reliability on 65nm Technology

2007 ◽  
Author(s):  
Pei-Haw Tsao ◽  
Bill Kiang ◽  
Kenneth Wu ◽  
Abel Chang ◽  
Tsorng-Dih Yuan
Keyword(s):  
Flip Chip ◽  
Board Level ◽  
Board Level Reliability ◽  
Low K

Package Qualification Envelope for 22FDX® Technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000169-000175
Author(s):  
Christian Klewer ◽  
Frank Kuechenmeister ◽  
Jens Paul ◽  
Dirk Breuer ◽  
Bjoern Boehme ◽  
...  
Keyword(s):  
Flip Chip ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
Characterization Methods ◽  
Fully Depleted ◽  
Individual Market ◽  
The Individual ◽  
Key Aspects ◽  
Board Level ◽  
Board Level Reliability

Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

Cu Pillar Bumping Technology with Solder Alloy Versatility

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002360-002376
Author(s):  
Guy Burgess ◽  
Anthony Curtis ◽  
Tom Nilsson ◽  
Gene Stout ◽  
Theodore G. Tessier
Keyword(s):  
Solder Alloy ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Solder Paste ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Wide Range ◽  
Method Of Production ◽  
Board Level

There is considerable interest in the semiconductor industry regarding Cu pillar bumping for finer pitch flip chip and 3D packaging applications. A common Cu Pillar method of production incorporates a combined Cu plated post topped with a plated solder pillar cap, usually of a Sn or SnAg alloy. Compared with this, a unique method of Cu pillar bump production developed at FlipChip International, LLC (FCI) creates the solder cap by applying and reflowing a solder paste on top of the plated Cu post. This method of production offers several benefits; the most important include a broader solder alloy selection, better alloy control, and improved overall pillar height uniformity. FCI has qualified a wide range of Cu pillar bump sizes, heights and shapes including Cu pillar bumps for fine pitch applications as low as 35um pitch (NANOPillarTM). FCI's Cu pillar bump structures in overmolded SiP have passed JEDEC 22-A104C board level thermal cycle testing, JEDEC J-STD-20A MLS 3@260C, as well as other board level corrosion and shock testing. FCI has demonstrated capping Cu pillar bumps with a broad range of solder alloys tailored to specific application requirements.

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