Adaptive Hot-Spot Cooling of Integrated Circuits Using Digital Microfluidics

2005 ◽  
Author(s):  
Phil Paik ◽  
Vamsee K. Pamula ◽  
Krishnendu Chakrabarty
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
High Performance ◽  
Cooling System ◽  
Hot Spot ◽  
Digital Microfluidics ◽  
Ic Design ◽  
Spot Cooling ◽  
Digital Microfluidic

Thermal management is becoming an increasingly important issue in integrated circuit (IC) design. The ability to cool ICs is quickly reaching a limit with today’s package-level solutions. While a number of novel cooling methods have been introduced, many of which are microfluidic approaches, these methods are unable to adaptively address the uneven thermal profiles and hot-spots generated in high performance ICs. In this paper, we present a droplet-based digital microfluidic cooling system for ICs that can adaptively cool hot-spots through real-time reprogrammable flow. This paper characterizes the effectiveness of microliter-sized droplets for cooling by determining the heat transfer coefficient of a droplet shuttling back and forth in an open system over a hot-spot at various speeds. Cooling is found to be significantly enhanced at higher flow rates of droplets. In order to further enhance cooling, the effect of varying droplet aspect ratio (width/height) in a confined system was also studied.

Fluid-to-Fluid Spot-to-Spreader (F2/S2) Hybrid Heat Sink for Integrated Chip-Level and Hot Spot-Level Thermal Management

2009 ◽  
Vol 131 (2) ◽  
Author(s):  
Craig Green ◽  
Andrei G. Fedorov ◽  
Yogendra K. Joshi
Keyword(s):  
Integrated Circuits ◽  
Heat Sink ◽  
Cooling System ◽  
Hot Spot ◽  
Heat Fluxes ◽  
Close Coupling ◽  
Thermal Fluids ◽  
Spot Cooling ◽  
Dynamics Simulations ◽  
Heat Sink Design

An innovative heat sink design aimed at meeting both the hot spot and large background heat flux requirements of next generation integrated circuits is presented. The heat sink design utilizes two separate unmixed fluids to meet the cooling requirements of the chip with one fluid acting as a fluidic spreader dedicated to cooling the hot spots only, while the second fluid serves as both a coolant for the background heat fluxes and an on-chip regenerator for the hot spot fluid. In this paper the conceptual heat sink design is presented and its theoretical capabilities are explored through optimization calculations and computational fluid dynamics simulations. It has been shown that through close coupling of the two thermal fluids the proposed hybrid heat sink can theoretically remove hot spot heat fluxes on the order of 1 kW/cm2 and background heat fluxes up to 100 W/cm2 in one compact and efficient package. Additionally, it has been shown that the F2/S2 design can handle these thermal loads with a relatively small pressure drop penalty, within the realm of existing micropump technologies. Finally, the feasibility of the F2/S2 design was demonstrated experimentally by modifying a commercially available, air-cooled aluminum heat sink to accommodate an integrated hot spot cooling system and fluidic spreader. The results of these experiments, where the prototype heat sink was able to remove hot spot heat fluxes of up to 365 W/cm2 and background heat fluxes of up to 20 W/cm2, are reported.

scholarly journals The Chip Cooling Model and Route Optimization with Digital Microfluidics

2019 ◽  
Vol 37 (1) ◽  
pp. 107-113
Author(s):  
Shaoxi Wang ◽  
Yue Yin ◽  
Xiaoya Fan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Digital Microfluidics ◽  
Route Optimization ◽  
Uniform Heat Flux ◽  
Chip Cooling ◽  
Capacitance Performance ◽  
Cooling Model ◽  
Cooling Technique

Using microfluidic technology to achieve integrated chip cooling is becoming a promising method to extend Moore law effective period. The thermal management is always critical for 3D integrated circuit design. Hot spots due to spatially non-uniform heat flux in integrated circuits can cause physical stress that further reduces reliability. The critical point for chip cooling is to use microfluidic cooling accurately on the hot spots. First, based on electro-wetting on dielectric, the paper presents an adaptive chip cooling technique using the digital microfluidics. Then, a two-plans 3D chip cooling model has been given with its working principle and characteristics. And single plan chip cooling model is presented, including its capacitance performance and models. Moreover, the dentate electrode is designed to achieve droplet continuing movement. Next, the ant colony optimization is adopted to get optimal route during electrode moving. Last, the experiments demonstrate the adaptive chip cooling technique proposed in this paper is effective and efficiency.

Investigation of On-Chip Hot Spot Cooling Using Microchannel Heat Sink

2013 ◽  
Vol 455 ◽  
pp. 466-469
Author(s):  
Yun Chuan Wu ◽  
Shang Long Xu ◽  
Chao Wang
Keyword(s):  
Heat Flux ◽  
Heat Sink ◽  
Hot Spots ◽  
Hot Spot ◽  
High Heat ◽  
High Heat Flux ◽  
Microchannel Heat Sink ◽  
Three Dimensional Model ◽  
Spot Cooling ◽  
On Chip

With the increase of performance demands, the nonuniformity of on-chip power dissipation becomes greater, causing localized high heat flux hot spots that can degrade the processor performance and reliability. In this paper, a three-dimensional model of the copper microchannel heat sink, with hot spot heating and background heating on the back, was developed and used for numerical simulation to predict the hot spot cooling performance. The hot spot is cooled by localized cross channels. The pressure drop, thermal resistance and effects of hot spot heat flux and fluid flow velocity on the cooling of on-chip hot spots, are investigated in detail.

INTEGRATED CIRCUIT DESIGN RESEARCH RANKING FOR WORLDWIDE UNIVERSITIES

2008 ◽  
Vol 17 (01) ◽  
pp. 141-167 ◽  
Author(s):  
KIAT-SENG YEO ◽  
ZHI-HUI KONG ◽  
NUKALA NISHANT ◽  
HAITAO FU ◽  
WEI ZENG
Keyword(s):  
Integrated Circuits ◽  
Video Game ◽  
Integrated Circuit ◽  
Design Research ◽  
Research Performance ◽  
Ic Design ◽  
Skilled Manpower ◽  
Knowledge Intensive ◽  
Number Of Publications ◽  
Video Game Consoles

The proliferation of integrated circuits (ICs) in the present technological era has brought forth revolutionary digital modernization that has ultimately transformed the history and lifestyle of humankind. ICs have become the heart of practically all state-of-the-art electronic devices such as computers, cell phones, video game consoles, and cameras. This ever-flourishing IC design industry is knowledge-intensive, which in turn translates into a huge appetite for technically precocious talents. Hence, in an effort to fuel and further foster the industry with more highly skilled manpower and at the same time to vie for a share of the burgeoning industry, higher educational institutions and universities from all around the globe are placing greater than ever emphasis on IC design research. Most importantly, strenuous efforts in a holistic manner are being made by each university in order to elicit outstanding and top-notch research in IC design. The authors have conducted a detailed and extensive survey to rank the various universities of the world in the field of IC design based on their research performance. In fact, assessments in the form of ranking have gained prominence over the recent years captivating the attention of a large number of students and universities. It helps the students in knowing how each university is progressing in a particular field and in turn helps the universities in analyzing their positions globally to remain competitive. Three ranking indicators, namely the Number of Publications, Citation Counts, and Cites per Paper have been chosen. The methodology used in ranking is also reported. The universities occupying the top echelons in IC design research are identified and a proven three-pronged approach for eliciting outstanding research performance is discussed.

Layout Based Full Chip Thermal Simulations of Stacked 3D Integrated Circuits

2003 ◽  
Author(s):  
Ashok Raman ◽  
Marek Turowski ◽  
Monte Mar
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
3D Ic ◽  
Localized Heating ◽  
3D Integrated Circuits ◽  
Thermal Simulations

This paper presents full-chip scale detailed thermal simulations of three-dimensional (3D) integrated circuit (IC) stacks. The inter-layer dielectric (ILD) and inter-metal dielectric (IMD) materials inside 3D IC stacks may cause extensive localized heating. The influence of multiple layers of dielectrics on heat trapping inside the 3D stack is analyzed. Different methods to minimize such localized heating are studied. It is shown that the use of thermal vias is very effective in heat dissipation from the hot spots. Comparisons are made between several 3D IC configurations to verify these conclusions.

Modeling of Two-Phase Evaporative Heat Transfer in Three-Dimensional Multicavity High Performance Microprocessor Chip Stacks

2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Yassir Madhour ◽  
Brian P. d'Entremont ◽  
Jackson Braz Marcinichen ◽  
Bruno Michel ◽  
John Richard Thome
Keyword(s):  
Integrated Circuit ◽  
Hot Spots ◽  
High Performance ◽  
Three Dimensional ◽  
Flow Distribution ◽  
Simulation Method ◽  
Heat Fluxes ◽  
Signal Delay ◽  
Two Phase ◽  
Signal Delay Time

Three-dimensional (3D) stacking of integrated-circuit (IC) dies increases system density and package functionality by vertically integrating two or more dies with area-array through-silicon-vias (TSVs). This reduces the length of global interconnects and the signal delay time and allows improvements in energy efficiency. However, the accumulation of heat fluxes and thermal interface resistances is a major limitation of vertically integrated packages. Scalable cooling solutions, such as two-phase interlayer cooling, will be required to extend 3D stacks beyond the most modest numbers of dies. This paper introduces a realistic 3D chip stack along with a simulation method for the heat spreading and flow distribution among the channels of the evaporators. The model includes the significant sensitivity of each channel's friction factor to vapor quality, and hence mass flow to heat flux, which characterizes parallel two-phase flows. Simulation cases explore various placements of hot spots within the stack and effects which are unique to two-phase interlayer cooling. The results show that the effect of hot spots on individual dies can be mitigated by strong interlayer heat conduction if the relative position of the hot spots is selected carefully to result in a heat load and flow which are well balanced laterally.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

2011 ◽  
Author(s):  
Matthew Redmond ◽  
Kavin Manickaraj ◽  
Owen Sullivan ◽  
Satish Kumar
Keyword(s):  
Integrated Circuits ◽  
Thermal Management ◽  
Power Density ◽  
Hot Spot ◽  
Thermal Contact ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermoelectric Coolers ◽  
Vertical Coupling ◽  
Spot Cooling

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Removing the Hot-Spots in High Power Devices Using the Thermoelectric Cooler and Micro Heat Pipe

2012 ◽  
Author(s):  
Agat Hirachan ◽  
Dereje Agonafer
Keyword(s):  
Heat Pipe ◽  
Integrated Circuit ◽  
Hot Spots ◽  
Hot Spot ◽  
The United States ◽  
High Heat ◽  
Heat Fluxes ◽  
Thermoelectric Cooler ◽  
Silicon Chips ◽  
Micro Heat Pipe

Due to localized high heat fluxes, hot-spots are created in silicon chips. Cooling of the hot-spots is one of the major thermal challenges in today’s integrated circuit (IC) industry. Many researches have been conducted to find ways to cool hot-spots using different techniques as uniform heating is highly desired. This paper focuses on cooling of hot-spot using conventional thermoelectric cooler (Melcor_CP1.0-31-05L.1) and a micro heat pipe. A chip package with conventional integrated heat spreader and heat sink was designed. Hot-spot was created at the center of the silicon die with background heat at rest of the area. The heat flux on the hot-spot was much greater than rest of the area. Forced convection was used to cool IC package, temperature was observed at active side of the silicon die. After that a copper conductor was used to take away heat directly from the hot-spot of the silicon die to the other end of the conductor which was cooled using the thermoelectric cooler. Finally the conductor was replaced by a heat pipe and a comparison between three cases was done to study the cooling performance using the commercial software, ANSYS Icepak. The effect of trench on silicon die was also studied. In this paper the United States Patent, Patent No. US 6,581,388 B2, Jun. 24 2000 [8] as shown in Fig. 1 (b) was modified by replacing the conductor with a micro heat pipe to solve the hot-spots problem in electronic packaging.

Optimization of Thermoelectric Coolers for Hotspot Cooling in Three-Dimensional Stacked Chips

2014 ◽  
Vol 137 (1) ◽  
Author(s):  
Matthew Redmond ◽  
Satish Kumar
Keyword(s):  
Power Consumption ◽  
Power Distribution ◽  
Hot Spots ◽  
Cooling System ◽  
Hot Spot ◽  
Three Dimensional ◽  
Optimization Methods ◽  
Thermoelectric Coolers ◽  
Robust Solution ◽  
3D Chip Stacking

Three-dimensional (3D) chip stacking architecture is expected to reduce form factor, improve performance, and decrease power consumption in future microelectronics. High power density and nonuniform power distribution in stacked dies are expected to bring significant thermal challenges for 3D packages due to localized hot spots. Embedded thermoelectric coolers (TECs) have potential to provide reliable and localized cooling at these hot spots. In this work, peak package temperature or active cooling per power consumption of TECs are optimized, considering applied current and thickness of TECs as parameters, for a 3D electronic package with two stacked dies. Each die has two hot spots and one TEC is paired with each hot spot. Three different optimization methods are considered in order to ensure a robust solution. The optimization suggests that both the peak temperature in package and energy efficiency of the cooling system can be significantly improved through the optimization of TECs. TECs are also compared against a configuration where they are replaced by copper blocks or thermal vias. A total of 4.7 °C of additional localized cooling is observed using TECs which is beyond what is achievable with copper vias in place of the TECs. The study also suggests that it is better to use TECs to cool only the hottest portions of the package to avoid introducing additional thermal resistance and Joule heating in the package.

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