Several Failure Analysis Cases of Pressure Equipment Under the Conditions of Complex Medium Environment

2011 ◽  
Author(s):  
Xuedong Chen ◽  
Zhibin Ai ◽  
Tiecheng Yang ◽  
Zhichao Fan ◽  
Weihe Guan
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Preventive Measures ◽  
Effective Means ◽  
Failure Mechanisms ◽  
Pressure Vessels ◽  
Influential Factors ◽  
Complex Medium ◽  
Complex Environment ◽  
Failure Prevention

There are several hundred of failure cases of pressure vessels and piping in China every year. The causes for part of accidents have been clearly analyzed, and preventive measures have been taken making the similar accidents substantially reduced, but the causes for quite a few failure accidents are still not found effectively, the similar accidents is still taking place. Through study, the authors find that the major reason for deviation of failure analysis lies in that equipments are mostly operating in complex medium environment, and mutual competition may exist among multiple failure mechanisms. Sometimes changes of some influential factors may cause the dominant failure mechanism change, even leads to totally different analysis conclusions. Combining with the analysis and verification of several failure cases of pressure vessels and piping in petrochemical enterprises, the judgment method for the dominant failure mechanism under multiple failure mechanisms is discussed in this paper, which may be helpful to provide some effective means for failure prevention of pressure equipment under complex environment.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Discussion on the Interference Phenomenon of Multiple Failure Mechanisms and Determination of Dominant Failure Mechanism for Pressure Equipments

2016 ◽  
Author(s):  
Chen Xuedong ◽  
Ai Zhibin ◽  
Li Rongrong ◽  
Fan Zhichao ◽  
Xu Shuangqing ◽  
...  
Keyword(s):  
Stainless Steel ◽  
Austenitic Stainless Steel ◽  
Failure Mechanism ◽  
Failure Mechanisms ◽  
Pressure Vessels ◽  
Intergranular Stress Corrosion ◽  
Interference Phenomenon ◽  
Corrosion Failure ◽  
Media Environment

For petrochemical pressure vessels subjected to complex media environment, the competition, inhibition, promotion and interference of multiple failure mechanisms have been discussed by several failure case analyses and experimental investigation. The main factors that influence formation of dominant failure mechanism are analyzed and the judgment principles of the dominant failure mechanism are raised in the case of interaction of multiple failure mechanisms. In this paper, relevant mechanisms are also discussed, e.g. intergranular corrosion and intergranular stress corrosion failure mechanisms of austenitic stainless steel, failure mechanisms of austenitic stainless steel when Cl− and alkaline environment exist concurrently and failure mechanism of austenitic stainless steel when medium such as Cl−, CO2, H2S, H2O, etc. exist concurrently.

Two Unique Case Studies Performed With Photoemission Microscopy (PEM)

1996 ◽  
Author(s):  
G.F. Shade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Current Flow ◽  
Failure Mechanisms ◽  
Analysis Time ◽  
Unique Case ◽  
Qualitative Evidence ◽  
Leakage Path

Abstract Two cases are presented where photoemission microscopy (PEM) quickly reduced the analysis time by providing qualitative evidence of the suspected failure mechanisms. In both cases, the failures were delaying product shipments and the PEM technique was a "last hope" approach where other proposals were either not successful, or were not available to the analysts. In case one, package residue caused a leakage path that was located and confirmed by PEM. The second case required the use of PEM to observe uniformity of current flow within a polysilicon region. This second analysis provided absolute evidence that the current flow was nonuniform which supported the suspected failure mechanism. It is believed that this is the first reported observation of these two emission mechanisms during a failure analysis.

Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies

2018 ◽  
Author(s):  
Zhigang Song
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Process Variation ◽  
Failure Mechanisms ◽  
Semiconductor Technology ◽  
New Materials ◽  
Analysis Methodology ◽  
Scaling Down ◽  
Nanometer Regime

Abstract As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

On the role of tin underlays for the prevention of thermal grooving in thin gold films

1986 ◽  
Vol 44 ◽  
pp. 732-733
Author(s):  
Jin Young Kim ◽  
R. E. Hummel ◽  
R. T. DeHoff
Keyword(s):  
Thin Film ◽  
Free Surface ◽  
Grain Boundary ◽  
Beneficial Effect ◽  
Failure Mechanism ◽  
Failure Mechanisms ◽  
Distinct Advantage ◽  
Gold Films ◽  
Gold Thin Film

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique

2008 ◽  
Author(s):  
Suk Min Kim ◽  
Jung Ho Lee ◽  
Jong Hak Lee ◽  
Hyung Ki Kim ◽  
Myung Sick Chang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Electrical Characteristics ◽  
The Future ◽  
Electrical Analysis

Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.

Advanced IR-OBIRCH Analysis Technique for High Isb Failure Analysis

2010 ◽  
Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Fault Localization ◽  
Resistance Change ◽  
The Real ◽  
Analysis Techniques ◽  
Analysis Technique ◽  
Leakage Failure ◽  
Failure Site

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

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