RECENT PROGRESS ON GaN-BASED ELECTRON DEVICES

2006 ◽  
Vol 16 (02) ◽  
pp. 469-477
Author(s):  
Yasuhiro Uemoto ◽  
Yutaka Hirose ◽  
Tomohiro Murata ◽  
Hidetoshi Ishida ◽  
Masahiro Hikita ◽  
...  
Keyword(s):  
Noise Figure ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Low Noise ◽  
60 Ghz ◽  
Si Doping ◽  
Power Handling Capability ◽  
Source Resistance ◽  
State Breakdown ◽  
A Current

We present results of some novel AlGaN/GaN heterojunction field-effect transistors (HFETs) specifically developed for RF front-end and power applications. To reduce the parasitic resistance, two unique techniques: selective Si doping into contact area and a superlattice (SL) cap structure, are developed. With the selective Si doping method, a transistor with an on-state resistance as low as 1.86 Ω·mm and a Tx/Rx switch IC with very low insertion loss (0.26 dB) and very high power handling capability (P1dB over 40 dBm) were obtained. With the SL cap HFETs, an ultra low source resistance of 0.4 Ω·mm was achieved and excellent DC and RF performances were demonstrated. The typical characteristics of these HFETs are: maximum transconductance of over 400 mS/mm, maximum drain current of 1.2 A/mm, cut-off frequency of 60 GHz, maximum oscillation frequency of 140 GHz, and a very low noise figure of 0.7 dB with 15 dB gain at 12 GHz. For power applications, in order to significantly reduce fabrication cost, we fabricated the AlGaN/GaN HFET on a conductive Si substrate with a source-via grounding (SVG) structure. The device has a very low on-state sheet resistance of 1.9 mΩ·cm2, a high off-state breakdown voltage of 350 V, and a current handling capability of 150 A. In addition, a sub-nano second switching response with t r of 98 ps and t f of 96 ps with a current density as high as 2.0 kA/cm2 is demonstrated for the first time.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals High drain-current-density and high breakdown-field Al0.36Ga0.64N-channel heterojunction filed-effect transistors with a dual AlN/AlGaInN barrier layer

2022 ◽  
Author(s):  
Akiyoshi Inoue ◽  
Sakura Tanaka ◽  
Takashi Egawa ◽  
Makoto Miyoshi
Keyword(s):  
Current Density ◽  
Barrier Layer ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Device Fabrication ◽  
Breakdown Field ◽  
Field Plate ◽  
Order Of Magnitude ◽  
State Breakdown

Abstract In this study, we fabricated and characterized heterojunction field-effect transistors (HFETs) based on an Al0.36Ga0.64N-channel heterostructure with a dual AlN/AlGaInN barrier layer. The device fabrication was accomplished by adopting a regrown n++-GaN layer for ohmic contacts. The fabricated HFETs with a gate length of 2 μm and a gate-to-drain distance of 6 μm exhibited an on-state drain current density as high as approximately 270 mA/mm and an off-state breakdown voltage of approximately 1 kV, which corresponds to an off-state critical electric field of 166 V/μm. This breakdown field, as a comparison in devices without field-plate electrodes, reaches approximately four-fold higher than that for conventional GaN-channel HFETs and was considered quite reasonable as an Al0.36Ga0.64N-channel transistor. It was also confirmed that the devices adopting the dual AlN/AlGaInN barrier layer showed approximately one order of magnitude smaller gate leakage currents than those for devices without the top AlN barrier layer.

SILICON-BASED INTEGRATED MOSFETS AND MESFETS: A NEW PARADIGM FOR LOW POWER, MIXED SIGNAL, MONOLITHIC SYSTEMS USING COMMERCIALLY AVAILABLE SOI

2006 ◽  
Vol 16 (02) ◽  
pp. 723-732 ◽  
Author(s):  
JINMAN YANG ◽  
ASHA BALIJEPALLI ◽  
TREVOR J. THORNTON ◽  
JAMES VANDERSAND ◽  
BENJAMIN J. BLALOCK ◽  
...  
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Field Effect Transistors ◽  
Circuit Simulation ◽  
Drain Current ◽  
Low Noise ◽  
Measured Data ◽  
Silicon On Insulator ◽  
New Paradigm ◽  
Mixed Signal

Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data.

The Impact of the Extrinsic Device on HFET Performance

1991 ◽  
Vol 240 ◽  
Author(s):  
David R. Greenberg ◽  
Jesús A. Del Alamo
Keyword(s):  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Insulator ◽  
Figures Of Merit ◽  
Velocity Saturation ◽  
Heterostructure Field Effect Transistors ◽  
Source Resistance ◽  
Carrier Velocity ◽  
The Impact ◽  
Ultimate Limit

ABSTRACTThe extrinsic device is known to degrade the performance of heterostructure field-effect transistors (HFET's) through the introduction of a parasitic source resistance (Rs). To date, however, there has been no recognition of the fact that carrier velocity saturation (vsat) can occur in both the extrinsic source and drain, setting the ultimate limit on maximum drain current (I,D,max) and on the useful VGS swing in HFET's. In this study, we demonstrate the mechanisms through which vsat in the extrinsic device limits device performance, using AlGaAs/n+-InGaAs Metal-Insulator-Doped-channel FET's (MIDFET's) as a vehicle. These devices show that gm falls at a lower VGSthan does fT, by as much as 1 V. This reveals that there are two mechanisms at work. The approach of vsat in the extrinsic source first causes the small-signal source resistance (Ts)to rise rapidly, leading gm to decline but leaving fT unaffected. As the carrier velocity in the extrinsic device approaches Vsat more closely, there is an actual decline of the carrier velocity in the intrinsic device. This process degrades velocity-related figures of merit such as and fT.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

Materials and Device Characteristics of InAlAs/InGaAs HEMTs

1992 ◽  
Vol 281 ◽  
Author(s):  
Pin Ho ◽  
M. Y. Kao ◽  
P. C. Chao ◽  
K. H. G. Duh ◽  
P. M. Smith ◽  
...  
Keyword(s):  
Power Density ◽  
Output Power ◽  
Electron Mobility ◽  
Noise Figure ◽  
Low Noise ◽  
Maximum Output ◽  
High Electron ◽  
60 Ghz ◽  
Power Gain ◽  
Power Added Efficiency

ABSTRACTHigh electron mobility transistors (HEMTs) based on the InAlAs/InGaAs heterostructure have been grown on InP by molecular beam epitaxy. At room temperature, typical sheet charge densities of 2.1–3.0×1012 cm−2 and Hall electron mobilities over 10000 cm2 /V-s are obtained. An electron mobility as high as 13000 cm2 /V-s is achieved with a pseudomorphic Iny Ga1−y As channel and a y value of 0.70.HEMTs with a T- or Γ-shaped gate and with gate lengths ranging from 0.1–0.25 urn have been fabricated. A record low noise figure of 0.7 dB with an associated gain of 8.6 dB at 62 GHz has been achieved with 0.1 μm Γ-gate devices, while T-gate devices exhibit a minimum noise figure of 1.2 dB with 7.2 dB associated gain at 94 GHz. Separately, a record fmax value of 455 GHz was determined by extrapolating at -6 dB/octave from the measured gain of 13.6 dB at 95 GHz.Power HEMTs using a double heterojunction structure exhibit a record peak power-added efficiency (P.A.E.) of 49% with 8.6 dB power gain and 0.30 W/mm power density measured at 60 GHz. When biased and tuned for maximum output power, our best 60 GHz output power density to date is 0.52 W/mm with 33% P.A.E. and 5.9 dB power gain using a single heterojunction HEMT scheme with pseudomorphic channel. A similar device also yields peak P.A.E. of 26% with 0.20 W/mm power density and 4.9 dB gain at 94 GHz. These results represent the highest P.A.E.S and power gains ever reported for any transistor at these frequencies.

scholarly journals Computation of Constant Gain and NF Circles for 60 GHz Ultra-low noise Amplifiers

2021 ◽  
Vol 3 (3) ◽  
pp. 146-156
Author(s):  
Christina Gnanamani ◽  
Shanthini Pandiaraj
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Communication Link ◽  
60 Ghz ◽  
Output Impedance ◽  
Maximum Value ◽  
Input Module ◽  
Ultra Low Noise ◽  
Constant Source

Wireless communication is a constantly evolving and forging domain. The action of the RF input module is critical in the radio frequency signal communication link. This paper discusses the design of a RF high frequency transistor amplifier for unlicensed 60 GHz applications. The Transistor used for analysis is a FET amplifier, operated at 60GHz with 10 mA at 6.0 V. The simulation of the amplifier is made with the Open Source Scilab 6.0.1 console software. The MESFET is biased such that Sll = 0.9<30°, S12 = 0.21<-60°, S21= 2.51<-80°, and S22 = 0.21<-15o. It is found that the transistor is unconditionally stable and hence unilateral approximation can be employed. With these assumptions, the maximum value of source gain of the amplifier is found to be at 7.212 dB and the various constant source gain circles and noise figure circles are computed. The transistor has the following noise parameters: Fmin = 3 dB, Rn = 4 Ω, and Γopt = 0.485<155°. The amplifier is designed to have an input and output impedance of 50 ohms which is considered as the reference impedance.

scholarly journals Design, Analysis and Measurement Results of a Fully-Integrated Low-power LNA Presenting Faults

2013 ◽  
Vol 8 (1) ◽  
pp. 32-42
Author(s):  
Paulo M. Moreira e Silva ◽  
Fernando Rangel de Sousa
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Fully Integrated ◽  
Uncertainty Sources ◽  
Measurement Results ◽  
Noise Amplifier ◽  
A Current ◽  
Measured Input

We present in this paper the analysis, design and measurement results of a low noise amplifier (LNA) operating in the ISM band at 2.45 GHz. The circuit topology adopted was based on a current reuse technique to minimize the power consumption. A prototype was fabricated in a 0.18-μm standard CMOS technology and the measured power consumption was 1.1 mW. The measured input reflection coefficient was below -10 dB and the reverse isolation was higher than 20 dB. The measured insertion gain and noise figure were 5.6 dB and 4.8 dB respectively, with divergences from the simulated values of 5 dB and 2 dB, respectively. To explain these discrepancies, we devised an analysis on the circuit, including sources of uncertainties. Moreover, we characterized a transistor included in the LNA die, that helped to explain part of the disagreements. After including the uncertainty sources, we wereaable to explain a deviation of 3.9 dB in the insertion gain with respect to the simulated result.

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