DYNAMIC GaAs LOGIC CIRCUITS

1991 ◽  
Vol 02 (03) ◽  
pp. 163-183
Author(s):  
DAVID H.K. HOE ◽  
C. ANDRE T. SALAMA
Keyword(s):  
Power Dissipation ◽  
Clock Cycle ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
System Throughput ◽  
Leakage Currents ◽  
Design And Implementation ◽  
Main Challenge ◽  
Dynamic Circuits ◽  
Functional Blocks

Because of their ratioless nature, dynamic logic has several advantages over conventional static techniques used in GaAs . The ability to implement complex gates with dynamic logic leads to circuits with increased speed and reduced power dissipation. Several dynamic configurations using GaAs MESFETs are reviewed. The main challenge is to overcome leakage currents associated with the Schottky gate junctions in order to allow reliable dynamic operation. The pipelining of GaAs dynamic circuits, which allows full use of the clock cycle and improves system throughput, is also discussed. The feasibility of using these dynamic designs in GaAs is illustrated through the design and implementation of complex functional blocks.

scholarly journals Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic

2017 ◽  
Vol 6 (2) ◽  
pp. 122-132
Author(s):  
Deepika Bansal ◽  
Brahmadeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Performance Improvement ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Charge Sharing ◽  
Domino Logic ◽  
Dynamic Circuits ◽  
Low Power Dissipation ◽  
High System ◽  
Domino Circuits

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.

scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies

2016 ◽  
Vol 13 (10) ◽  
pp. 6999-7008
Author(s):  
N Anusha ◽  
T Sasilatha
Keyword(s):  
Comparative Analysis ◽  
Performance Analysis ◽  
Metal Oxide ◽  
Leakage Current ◽  
Power Dissipation ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Oxide Semiconductors ◽  
Dynamic Circuits

Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Design and Implementation of LCG-Trivium Key Stream Generator into FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 186
Author(s):  
Tchahou Tchendjeu A. E ◽  
Tchitnga Robert ◽  
Fotsin Hilaire B
Keyword(s):  
Stream Cipher ◽  
Clock Cycle ◽  
State Machine ◽  
Initial Value ◽  
Design And Implementation ◽  
Generator Circuit ◽  
Quartus Ii ◽  
Initialization Vector ◽  
Linear Congruential Generator ◽  
Linear Congruential

<p>This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 2<sup>64</sup> clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2<sup>144</sup> bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.</p>

Nmos Logic Circuits in Laser-Crystallized Silicon on Quartz

1983 ◽  
Vol 23 ◽  
Author(s):  
A. Chiang ◽  
M. H. Zarzycki ◽  
W. P. Meuli ◽  
N. M. Johnson
Keyword(s):  
High Performance ◽  
Logic Circuits ◽  
Leakage Currents ◽  
Enhancement Mode ◽  
Low Leakage ◽  
Fused Quartz ◽  
Amorphous Substrates ◽  
Circular Beam ◽  
Processing Steps ◽  
Dynamic Shift

ABSTRACTDepletion mode as well as enhancement mode n-channel thin-film transistors (TFT's) have been fabricated in CO2 laser-crystallized silicon on fused quartz. Nearly defect-free islands were obtained by using an offset circular beam to form a tilted melt interface. The optimization of subsequent processing steps to achieve simultaneously low leakage currents and voltage thresholds appropriate for depletion-load NMOS circuits involved adjustments of ion implantation and high temperature cycles with the aid of simulation. The resultant high performance silicon-gate TFT's have led to NMOS ring oscillators with 2.5 ns delay/stage and dynamic shift registers with MHz clock rates. These are the first logic circuits fabricated in beam-crystallized silicon on bulk amorphous substrates.

Sign in / Sign up

Export Citation Format

Share Document