A low power-integrated temperature sensor interface circuit

2022 ◽  
Author(s):  
Mingyuan Ren ◽  
Huijing Yang ◽  
Beining Zhang ◽  
Guoxu Zheng
Keyword(s):  
Temperature Sensor ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Average Power ◽  
Temperature Sensitive ◽  
Frequency Noise ◽  
Power Supply Voltage ◽  
Sensor Interface ◽  
Interface Circuit ◽  
Average Power Consumption

This paper constructs and simulates the interface circuit of a temperature sensor based on SMIC 0.18 [Formula: see text]m CMOS. The simulation results show that when the power supply voltage is 1.8 V, the chopper op-amp gain is 89.44 dB, the low-frequency noise is 71.83 nV/Hz,[Formula: see text] and the temperature coefficient of the core temperature sensitive circuit is 1.7808 mV/[Formula: see text]C. The sampling rate of 10-bit SAR ADC was 10 kS/s, effective bit was 9.0119, SNR was 59.3256 dB, SFDR was 68.7091 dB, and THD was −62.5859 dB. The measurement range of temperature sensor interface circuit is −50[Formula: see text]C[Formula: see text]C, the relative temperature measurement error is ±0.47[Formula: see text]C, the resolution is 0.2[Formula: see text]C/LSB, and the overall average power consumption is 434.9 [Formula: see text]W.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (3) ◽  
pp. 3037-3045
Author(s):  
M. Naga Gowtham Et.al
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

2021 ◽  
Vol 12 (5) ◽  
pp. 92-100
Author(s):  
M. Naga Gowtham, P.S Hari Krishna Reddy, K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
Transmission Gate ◽  
Average Power Consumption ◽  
Pass Transistor ◽  
Pass Transistor Logic

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

scholarly journals A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  
Keyword(s):  
Power Consumption ◽  
Temperature Sensor ◽  
Current Source ◽  
Average Power ◽  
Bias Current ◽  
Cmos Process ◽  
Linear Temperature ◽  
Temperature Characteristics ◽  
Period Ratio ◽  
Average Power Consumption

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sandeep Garg ◽  
Tarun Kumar Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Maximum Delay ◽  
Average Power Consumption

Purpose This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis. Design/methodology/approach In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE. Findings The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques. Originality/value The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

ANALYSIS OF VOLTAGE, CURRENT AND ENERGY DISSIPATION OF STEPWISE ADIABATIC CHARGING OF A CAPACITOR USING A NONRESONANT INDUCTOR CURRENT

2014 ◽  
Vol 23 (03) ◽  
pp. 1450039 ◽  
Author(s):  
SHUNJI NAKATA ◽  
HIROSHI MAKINO ◽  
RYOTA HONDA ◽  
MASAYUKI MIYAMA ◽  
YOSHIO MATSUDA
Keyword(s):  
Energy Dissipation ◽  
Power Supply ◽  
Supply Voltage ◽  
Average Power ◽  
Power Supply Voltage ◽  
Switching Transistor ◽  
Analytical Resolution ◽  
A Current ◽  
Transistor Circuit ◽  
Matrix Calculation

This paper describes characteristics of stepwise adiabatic charging with an inductor current by controlling switching transistors. An exact analytical resolution is obtained by using a vector comprising a voltage and a current. From a matrix calculation, the voltage and current can be written with solutions of the characteristic equation, power supply voltage, the switching ratio in the switching transistor circuit, and the number of switchings. Using the expression, the voltage and current in the stepwise adiabatic charging method can be derived clearly. As a result, it is clarified analytically that, in N-step charging, the current is reduced to 1/N so that the energy dissipation is reduced to 1/N. Next, the experimental switching transistor circuit with the controller is described, which is composed of discrete ICs. The experimental inductor current in the circuit is investigated. The measured current is reduced to 1/N in N-step charging, which is consistent with the simulated one from the theory. It is also confirmed experimentally from the average power supply current that power consumption is reduced to 1/N.

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips

2018 ◽  
Vol 27 (09) ◽  
pp. 1850146 ◽  
Author(s):  
Alak Majumder ◽  
Pritam Bhattacharjee ◽  
Tushar Dhabal Das
Keyword(s):  
Supply Voltage ◽  
Average Power ◽  
Clock Gating ◽  
Power Supply Voltage ◽  
Silicon Chips ◽  
Current Ramp ◽  
Instantaneous Current ◽  
Bond Pads ◽  
Ground Noise ◽  
Circuit Configuration

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current [Formula: see text] and current ramp [Formula: see text]. To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of [Formula: see text] and [Formula: see text], thereby subduing PGN. The new CG arrangement is simulated for 90[Formula: see text]nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of [Formula: see text] and 84.19% of average [Formula: see text] in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90[Formula: see text]nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average [Formula: see text] and average power, respectively, to illustrate its capability of truncating PGN in silicon chips.

scholarly journals A customizable, low-power, wireless, embedded sensing platform for resistive nanoscale sensors

2022 ◽  
Vol 8 (1) ◽  
Author(s):  
Stefan Nedelcu ◽  
Kishan Thodkar ◽  
Christofer Hierold
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Limit Of Detection ◽  
Sampling Rate ◽  
Average Power ◽  
Physical Parameters ◽  
Embedded Sensing ◽  
Sensing Applications ◽  
Measurement Protocol ◽  
Average Power Consumption

AbstractCustomizable, portable, battery-operated, wireless platforms for interfacing high-sensitivity nanoscale sensors are a means to improve spatiotemporal measurement coverage of physical parameters. Such a platform can enable the expansion of IoT for environmental and lifestyle applications. Here we report a platform capable of acquiring currents ranging from 1.5 nA to 7.2 µA full-scale with 20-bit resolution and variable sampling rates of up to 3.125 kSPS. In addition, it features a bipolar voltage programmable in the range of −10 V to +5 V with a 3.65 mV resolution. A Finite State Machine steers the system by executing a set of embedded functions. The FSM allows for dynamic, customized adjustments of the nanosensor bias, including elevated bias schemes for self-heating, measurement range, bandwidth, sampling rate, and measurement time intervals. Furthermore, it enables data logging on external memory (SD card) and data transmission over a Bluetooth low energy connection. The average power consumption of the platform is 64.5 mW for a measurement protocol of three samples per second, including a BLE advertisement of a 0 dBm transmission power. A state-of-the-art (SoA) application of the platform performance using a CNT nanosensor, exposed to NO2 gas concentrations from 200 ppb down to 1 ppb, has been demonstrated. Although sensor signals are measured for NO2 concentrations of 1 ppb, the 3σ limit of detection (LOD) of 23 ppb is determined (1σ: 7 ppb) in slope detection mode, including the sensor signal variations in repeated measurements. The platform’s wide current range and high versatility make it suitable for signal acquisition from resistive nanosensors such as silicon nanowires, carbon nanotubes, graphene, and other 2D materials. Along with its overall low power consumption, the proposed platform is highly suitable for various sensing applications within the context of IoT.

scholarly journals High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

2016 ◽  
Vol 6 (1) ◽  
pp. 90
Author(s):  
Veepsa Bhatia ◽  
Neeta Pandey ◽  
Asok Bhattacharyya
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mode ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Power Efficient ◽  
Current Comparator ◽  
Average Power Consumption

A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

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