DERIVATION OF TRADE-OFF OF EQUATION FOR CMOS CROSS-COUPLED LC DIFFERENTIAL OSCILLATOR

2013 ◽  
Vol 22 (09) ◽  
pp. 1340002
Author(s):  
NIKORN HEN-NGAM ◽  
JIRAYUTH MAHATTANAKUL
Keyword(s):  
Process Parameters ◽  
Oscillation Frequency ◽  
Bias Current ◽  
Cmos Process ◽  
Time Varying ◽  
Performance Parameters ◽  
Trade Off ◽  
Circuit Simulator ◽  
Periodic Noise ◽  
Noise Simulation

This paper aims at presenting an equation describing a relation between power consumption and phase noise of the widely used CMOS cross-coupled LC differential oscillator. This equation is derived by using periodic time-varying method and it relates oscillator's key performance parameters, e.g., oscillation frequency and amplitude, sideband spectrum and bias current, and CMOS process parameters. The validity of the proposed equation was confirmed by the periodic noise simulation available in the Cadence's Virtuoso Spectre Circuit Simulator.

scholarly journals OTRA Based Voltage Mode Third Order Quadrature Oscillator

2014 ◽  
Vol 2014 ◽  
pp. 1-5 ◽  
Author(s):  
Rajeshwari Pandey ◽  
Neeta Pandey ◽  
Gurumurthy Komanapalli ◽  
Rashika Anurag
Keyword(s):  
Process Parameters ◽  
High Frequency ◽  
Oscillation Frequency ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Third Order ◽  
Linear Region ◽  
Fully Integrated ◽  
Electronic Tuning ◽  
Quadrature Oscillators

Two topologies of operational transresistance (OTRA) based third order quadrature oscillators (QO) are proposed in this paper. The proposed oscillators are designed using a combination of lossy and lossless integrators. The proposed topologies can be made fully integrated by implementing the resistors using matched transistors operating in linear region, which also facilitates electronic tuning of oscillation frequency. The nonideality analysis of the circuit is also given and for high frequency applications self-compensation can be used. Workability of the proposed QOs is verified through PSPICE simulations using 0.5 μm AGILENT CMOS process parameters. The total harmonic distortion (THD) for both the QO designs is found to be less than 1%.

Active Control of Fabricating Nanofibrous Wavy/Helical Arrays Using Near-Field Electrospinning

2018 ◽  
Author(s):  
Xiangyu You ◽  
Ping Guo
Keyword(s):  
Active Control ◽  
Process Parameters ◽  
Electric Field Distribution ◽  
Structural Parameters ◽  
Near Field ◽  
Stretchable Electronics ◽  
Time Varying ◽  
Photovoltaic Devices ◽  
Feature Size ◽  
Experimental Process

A novel and simple near-field electrospinning (NFES) method has been developed to fabricate wavy or helical nanofibrous arrays. By alternating the electrostatic signals applied on auxiliary-electrodes (AE), the structural parameters of deposited patterns can be actively controlled. Compared with the traditional electrospinning methods based on the bending and buckling effects or collector movement, the proposed method shows advantages in the controllability, accuracy, and minimal feature size. Forces operating on the electrospinning jet and the time-varying electric field distribution were analyzed to explain the kinematics of the jet. Nanoscale wavy and helical patterns with various structural parameters were fabricated. The effects of experimental process parameters on structural parameters of deposited patterns were analyzed to demonstrate the controllability of our method in fabricating wavy or helical nanofibrous structures. It is envisioned that this method will benefit the applications in the field of photovoltaic devices, sensors, transducers, resonators, and stretchable electronics.

scholarly journals A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  
Keyword(s):  
Power Consumption ◽  
Temperature Sensor ◽  
Current Source ◽  
Average Power ◽  
Bias Current ◽  
Cmos Process ◽  
Linear Temperature ◽  
Temperature Characteristics ◽  
Period Ratio ◽  
Average Power Consumption

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

A design procedure for improving the effectiveness of fractal layouts formation

2014 ◽  
Vol 28 (1) ◽  
pp. 1-26 ◽  
Author(s):  
Yung Chin Shih ◽  
Eduardo Vila Gonçalves Filho
Keyword(s):  
Design Procedure ◽  
Current Approach ◽  
Computational Time ◽  
Shop Floor ◽  
Processing Unit ◽  
Performance Parameters ◽  
Trade Off ◽  
Central Processing ◽  
Search Heuristics ◽  
Functional Layout

AbstractRecently, new types of layouts have been proposed in the literature in order to handle a large number of products. Among these are the fractal layout, aiming at minimization of routing distances. There are already researchers focusing on the design; however, we have noticed that the current approach usually executes several times the allocations of fractal cells on the shop floor up to find the best allocations, which may present a significant disadvantage when applied to a large number of fractal cells owing to combinatorial features. This paper aims to propose a criterion, based on similarity among fractal cells, developed and implemented in a Tabu search heuristics, in order to allocate it on the shop floor in a feasible computational time. Once our proposed procedure is modeled, operations of each workpiece are separated in n subsets and submitted to simulation. The results (traveling distance and makespan) are compared to distributed layout and to functional layout. The results show, in general, a trade-off behavior, that is, when the total routing distance decreases, the makespan increases. Based on our proposed method, depending on the value of segregated fractal cell similarity, it is possible to reduce both performance parameters. Finally, we conclude the proposed procedure shows to be quite promising because allocations of fractal cells demand reduced central processing unit time.

scholarly journals Performance Optimization of Visible Light Communication

2021 ◽  
Vol 9 ◽  
Author(s):  
Agha Yasir Ali ◽  
◽  
Lubna Farhi ◽  
Usama Ahmed ◽  
Asad Subhan ◽  
...  
Keyword(s):  
Visible Light ◽  
Bit Error Rate ◽  
Performance Optimization ◽  
Visible Light Communication ◽  
Data Rate ◽  
Modulation Scheme ◽  
Performance Parameters ◽  
Trade Off ◽  
High Bandwidth ◽  
Ber Performance

This paper focuses to analyze the data rate, bit error rate (BER), flickering & bandwidth of visible light communication (VLC) system. The existing modulation scheme ON-OFF Keying (OOK) is modified and produces the trade-off between these parameters. The modified ON-OFF Keying (MOOK) is proposed in which the variation in the transmitted pulses is investigated. Therefore, the square and rectangular pulses are used to transmit zero and one bits respectively. The duty cycle of square pulse is increased to improve the flickering performance. Moreover, it utilized the bandwidth and deteriorates the BER performance. The differential MOOK (DMOOK) modulation scheme is also proposed in which the ON period of square pulse (zero bits) is removed. Therefore, the data rate of DMOOK is increased because the duration of zero bit pulse is decreased. Similarly, the high bandwidth is utilized and BER performance deteriorates. All performance parameters are evaluated on Arduino based hardware VLC system. We conclude that the BER performance deteriorates by improving flickering performance and data rate of the VLC system.

scholarly journals Effect of changes in supply voltage on power consumption of digital CMOS delay lines

2016 ◽  
Vol 4 (4) ◽  
pp. 118-121
Author(s):  
Pankaj Prajapati ◽  
Dr. Shyam Akashe
Keyword(s):  
Power Consumption ◽  
Mobile Phones ◽  
Delay Line ◽  
Supply Voltage ◽  
Minimum Amount ◽  
Delay Lines ◽  
Performance Parameters ◽  
Digital Cmos ◽  
Trade Off ◽  
In The Beginning

In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.

scholarly journals Multiphysics Equivalent Circuit of a Thermally Controlled Hydrogel-Micro Valve

2015 ◽  
Author(s):  
Andreas Voigt ◽  
Uwe Marschner ◽  
Andreas Richter
Keyword(s):  
Equivalent Circuit ◽  
Time Delays ◽  
Elastic Moduli ◽  
Equivalent Circuit Model ◽  
Transient Behavior ◽  
Temperature Sensitive ◽  
Time Varying ◽  
Fluidic Channel ◽  
First Order ◽  
Circuit Simulator

Hydrogels consist of a network of cross-linked polymers that swell when put into water. For temperature-sensitive smart hydrogels the equilibrium hydrogel size depends on the temperature of the liquid. These hydrogels are used to build temperature-controlled fluidic valves. Here we present an equivalent circuit model of such a hydrogel valve. The transient behavior is based on the model by Tanaka with three additional assumptions: 1. Only the fundamental mode of the deformation field, i.e. the slowest-decaying exponential temporal behavior, is relevant. 2. There are distinct equilibrium sizes for the swollen and the de-swollen state. 3. As observed in experiment, the swollen gel and the de-swollen gel have different elastic moduli, which affect the time constants of swelling vs. de-swelling. The resulting network model includes three physical subsystems: the thermal subsystem, the polymeric subsystem and the fluidic subsystem. The thermal subsystem considers the temperature of the heater, of the adhesive and of the hydrogel. It is assumed that adhesive, housing and hydrogel act as heat capacities in combination with heat resistors. The modeled polymeric subsystem causes in addition time delays for swelling and de-swelling of first order with different delay constants. The fluidic subsystem basically includes the fluidic channel between hydrogel and housing with time varying cross section, which is modeled as controlled source. All subsystems are described and coupled within one single circuit. Thus the transient behavior of the hydrogel can be calculated using a circuit simulator. Simulation results for an assumed hydrogel setup are presented.

scholarly journals TiO2-x films for bolometer applications: recent progress and perspectives

2021 ◽  
Author(s):  
Qiming Zhang ◽  
Ruiyang Yan ◽  
Xiaoyan Peng ◽  
YuShui Wang ◽  
Shuanglong Feng
Keyword(s):  
Infrared Imaging ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Performance Parameters ◽  
Large Area ◽  
Temperature Coefficient Of Resistance ◽  
Sensitive Material ◽  
Good Thermal Stability ◽  
Photoelectric Performance

Abstract The bolometer is widely used in military and civilian infrared imaging due to its advantages of non-cooling, small size and portability. Thermosensitive materials seriously affect the performance of bolometers. As a kind of heat-sensitive material, the TiO2-x material has the advantages of good thermal stability, large-area preparation, and compatibility with the complementary metal-oxide semiconductor (CMOS) process. However, there is almost no review on the application of titanium oxide for bolometers. In this paper, we introduce the bolometer's main thermal and photoelectric performance parameters and the critical technologies to manufacture the bolometer. Finally, we will particularly emphasize the effects of preparation process parameters of TiO2 on the performance parameters temperature coefficient of resistance (TCR), 1/f noise, etc., were studied.

A 200 °C Quad-Output Buck Type Switched Mode Power Supply IC

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000022-000027
Author(s):  
Daniel T. Goff ◽  
Steve J. A. Majerus ◽  
Walter Merrill
Keyword(s):  
Power Supply ◽  
Oscillation Frequency ◽  
Low Cost ◽  
Bias Current ◽  
Buck Converter ◽  
Step Response ◽  
Level Shift ◽  
Output Current ◽  
Sensors And Actuators ◽  
Switched Mode Power Supply

A high temperature (>200 °C), quad-output, buck type switched-mode power supply (SMPS) IC capable of operating over a wide input supply range of 6 V to 15 V is described. The IC is a compact power supply solution for multi-voltage microprocessors, sensors, and actuators. The SMPS topology is a 112 kHz fixed-frequency, synchronous buck converter with slope compensation. A novel internal feedback design enables the output voltages to be pin-programmed to one of three common supply voltages—5 V, 3.3 V, or 1.8 V—while an external resistor divider can also be used for arbitrary voltage programming. Integrated power supply output MOSFET switches minimize the external part count and synchronous rectification reduces power dissipation and improves current capacity. The IC was fabricated in a conventional, low-cost, 0.5 μm bulk CMOS foundry process. Patented circuit design techniques allow the IC to operate in excess of 200 °C and circuit operation was demonstrated at ambient temperatures up to 225 °C. The foundry process is optimized for 5 V applications, however, the IC accepts input voltages up to 15 V and can produce outputs up to 10 V by utilizing extended drain single- and double-sided NMOS and PMOS transistors for the linear regulator pass transistor, error amplifier, and SMPS switches. The high-side FETs are controlled through capacitive coupled level shift circuits to ensure the gate-oxide voltage limits are not exceeded while still maintaining fast signal transitions. The IC also includes a tunable, 25 MHz monolithic oscillator that is programmable over a SPI serial interface. The oscillator bias current is comprised of a programmable constant-gm bias current and a programmable PTAT bias current. The programmability can be used to set the oscillation frequency, but can also be used together with a calibration curve on a microcontroller to achieve a more stable oscillation frequency over temperature. The output current of the quad SMPS was limited to 70 mA by a lower than expected saturation current of the extended-drain PMOS switch devices. The system showed good line regulation (<0.1%) and 50% load step response stability (+/− 100 mV) at a nominal output current of 50 mA when tested at 200 °C ambient.

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