A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology

2014 ◽  
Vol 513-517 ◽  
pp. 4572-4575
Author(s):  
Zhong Ying Zhu ◽  
Hui Hong ◽  
Shi Liang Li
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Fully Differential ◽  
Offset Voltage ◽  
High Speed Adc ◽  
Sine Signal ◽  
Low Offset

A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

2015 ◽  
Vol 24 (06) ◽  
pp. 1550093 ◽  
Author(s):  
Dengquan Li ◽  
Liang Zhang ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Single Channel ◽  
Mode Selection ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Timing Errors ◽  
Delay Locked Loop ◽  
Simulation Results ◽  
On Chip ◽  
Time Interleaved

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

scholarly journals DESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION

2014 ◽  
pp. 81-86
Author(s):  
SANTOSH KUMAR PATNAIK ◽  
DR. SWAPNA BANERJEE
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Power Supply ◽  
Cmos Technology ◽  
Sampling Frequency ◽  
Total Power ◽  
Digital Converter ◽  
Analog To Digital ◽  
Total Power Consumption ◽  
Single Power

This paper presents a new topology of an Analog-to-Digital Converter (ADC), named as Switched Reference ADC (SR-ADC) where the reference voltages are applied through switches. The switched reference voltage concept works with few mutually exclusive switches which are appropriately selecting the reference voltages for comparison with the input signal. This SR-ADC has been implemented using 0.18μm single poly and six metal CMOS technology. The spectra simulation result of this SR-ADC shows an ENOB of ≈3.53 for a 1V peak-to-peak input signal having a frequency of 100MHz while operating at a sampling frequency of 500MHz. The total power consumption is 21.39mW for a single power supply of 1.8V having a core area of ≈253μm*221μm.

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