High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

2015 ◽  
Vol 24 (09) ◽  
pp. 1550130 ◽  
Author(s):  
Yavar Safaei Mehrabani ◽  
Mohammad Eshghi
Keyword(s):  
Monte Carlo ◽  
High Frequency ◽  
High Speed ◽  
Transient Analysis ◽  
State Of The Art ◽  
Process Variations ◽  
Full Adder ◽  
The Other ◽  
Simulation Results ◽  
Silicon Based

In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (Design1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most efficient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results confirm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the most important concerns of nanoelectronics is studied using Monte Carlo transient analysis. This simulation reveals that Design3 functions very well against manufacturing process variations.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

scholarly journals A possible linear filtering model to explain White’s illusion at different grating widths

2017 ◽  
Author(s):  
Soma Mitra ◽  
Deabasis Mazumdar ◽  
Kuntal Ghosh ◽  
Kamales Bhaumik
Keyword(s):  
High Frequency ◽  
The Other ◽  
Linear Filtering ◽  
Multi Scale ◽  
Difference Of Gaussians ◽  
Frequency Components ◽  
Lightness Induction ◽  
Simulation Results ◽  
Model Support ◽  
Mach Band

The perceived lightness of a stimulus depends on its background, a phenomenon known as lightness induction. For instance, the same gray stimulus can look light in one background and dark in another. Moreover, such induction can take place in two directions; in one case, it occurs in the direction of the background lightness known as lightness assimilation, while in the other it occurs opposite to that, known as lightness contrast. The White’s illusion is a typical one which does not completely conform to any of these two processes. In this paper, we have quantified the perceptual strength of the White’s illusion as a function of the width of the background square grating. Based on our results which also corroborate some earlier studies, we propose a linear filtering model inspired from an earlier work dealing with varying Mach band widths. Our model assumes that the for the White’s illusion, where the edges are strong and many in number, and as such the spectrum is rich in high frequency components, the inhibitory surround in the classical Difference-of-Gaussians (DoG) filter gets suppressed, so that the filter essentially reduces to a multi-scale Gaussian one. The simulation results with this model support the present as well as earlier experimental results.

Development of Prediction Method for Wind Noise Caused by Airflow Around Front Pillar

2011 ◽  
Author(s):  
Yasuhiko Okutsu ◽  
Naoki Hamamoto ◽  
Robert Powell ◽  
Long Wu
Keyword(s):  
High Frequency ◽  
Noise Level ◽  
High Speed ◽  
Prediction Method ◽  
Noise Sources ◽  
Wind Noise ◽  
Front Passenger ◽  
Passenger Seat ◽  
Simulation Results ◽  
Head Area

To control high frequency wind noise upper than 1 kHz is important to ensure the comfort for a driver and passengers when vehicles cruise at high speed. Therefore the prediction method for high frequency wind noise inside a cabin has been required for development of a vehicle. This paper describes about the prediction method for high frequency wind noise from numerical simulation results. In this study, wind noise caused by airflow around a front pillar is predicted. We have predicted wind noise by visualizing noise sources and pressure fluctuation on vehicle surfaces in recent years. Although an inferior-to-superior relationship can be predicted from these results, it was difficult to estimate quantitative interior noise level. In this research, the SEA code is examined to predict such noise level. The SEA code has confirmed showing a qualitative and almost quantitative consistency of measured and calculated SPL at the head area of a front passenger seat.

Reservoir Simulation: Past, Present, and Future

1997 ◽  
Author(s):  
J. W. Watts
Keyword(s):  
Reservoir Simulation ◽  
State Of The Art ◽  
Simulation Software ◽  
The Other ◽  
Current State ◽  
Reservoir Development ◽  
Simulation Results ◽  
Historical Developments ◽  
The Right

Abstract Reservoir simulation is a mature technology, and nearly all major reservoir development decisions are based in some way on simulation results. Despite this maturity, the technology is changing rapidly. It is important for both providers and users of reservoir simulation software to understand where this change is leading. This paper takes a long-term view of reservoir simulation, describing where it has been and where it is now. It closes with a prediction of what the reservoir simulation state of the art will be in 2007 and speculation regarding certain aspects of simulation in 2017. Introduction Today, input from reservoir simulation is used in nearly all major reservoir development decisions. This has come about in part through technology improvements that make it easier to simulate reservoirs on one hand and possible to simulate them more realistically on the other; however, although reservoir simulation has come a long way from its beginnings in the 1950's, substantial further improvement is needed, and this is stimulating continual change in how simulation is performed. Given that this change is occurring, both developers and users of simulation have an interest in understanding where it is leading. Obviously, developers of new simulation capabilities need this understanding in order to keep their products relevant and competitive. However, people that use simulation also need this understanding; how else can they be confident that the organizations that provide their simulators are keeping up with advancing technology and moving in the right direction? In order to understand where we are going, it is helpful to know where we have been. Thus, this paper begins with a discussion of historical developments in reservoir simulation. Then it briefly describes the current state of the art in terms of how simulation is performed today. Finally, it closes with some general predictions.

Evaluation of PCB Shielding Characteristic in Near Field

2017 ◽  
Vol 5 (3) ◽  
pp. 542
Author(s):  
Yih Jian Chuah ◽  
Mohd Tafir Mustaffa
Keyword(s):  
Electromagnetic Interference ◽  
High Frequency ◽  
Near Field ◽  
Electronic Devices ◽  
The Other ◽  
Shielding Effectiveness ◽  
Electronic Industry ◽  
Common Solution ◽  
The Common ◽  
Simulation Results

Wireless electronic devices nowadays always operate in high frequency while having small and compact form factor which led to electromagnetic interference among traces and components. PCB shielding is the common solution applied in electronic industry to mitigate electromagnetic interference. In this paper, PCB shielding characteristics such as shield’s thickness, height, and ground via spacing in PCB boards were evaluated in near field. Test boards with various ground via spacing were fabricated and evaluated by using 3D Electromagnetic scanner. On the other hand, shields with various thickness and height were modeled and evaluated through simulation. Results suggested that shielding effectiveness could be improved by having greater shield’s height with smaller ground via spacing in shielding ground tracks. Shielding effectiveness can be improved by 1 dB with every step of 0.5 mm increase in shield’s height. Besides that, approximately 0.5 dB improvement in shielding effectiveness with every step of 1 mm decrease in ground via spacing. Furthermore, greater shield’s thickness can contribute better shielding effectiveness for operating frequency below 300 MHz.

scholarly journals Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-18 ◽  
Author(s):  
Subodh Wairya ◽  
Rajendra Kumar Nagaria ◽  
Sudarshan Tiwari
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Reducing Power ◽  
Full Adder ◽  
Process Models ◽  
Majority Function ◽  
Simulation Results

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

INTEGRATED SiGe AND Si DEVICE CAPABILITIES AND TRENDS FOR MULTI-GIGAHERTZ APPLICATIONS

2003 ◽  
Vol 13 (01) ◽  
pp. 175-219 ◽  
Author(s):  
G. G. FREEMAN ◽  
B. JAGANNATHAN ◽  
N. ZAMDMER ◽  
R. GROVES ◽  
R. SINGH ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
High Frequency ◽  
High Speed ◽  
Very High Frequency ◽  
Silicon Photodiode ◽  
Sige Hbt ◽  
Wide Range ◽  
On Chip ◽  
Silicon Based ◽  
Very High

Silicon-based devices, including the increasingly available SiGe-based devices, are now demonstrating fT and fMAX values over 200 GHz. These recent advances open the door to a wide range of silicon-based very high frequency, low power and highly integrated solutions. Trends in silicon MOS, SiGe HBT, SiGe MODFET and SiGe strained silicon FETs are reported. Silicon inroads to device functions viewed as the sole realm of III-V technologies are also being demonstrated. Capability and trends of the integrated silicon photodiode are reported here as an example. Integration of these high-speed devices into a complex circuit requires on-chip passive device functionality at such high frequency. Key devices to enable integration are the inductor, varactor, and transmission line, and operation of these devices at high frequency is reported. Further, we discuss noise isolation issues and techniques, which may be used when minimizing cross-talk within a conductive silicon substrate.

scholarly journals A possible linear filtering model to explain White’s illusion at different grating widths

2017 ◽  
Author(s):  
Soma Mitra ◽  
Deabasis Mazumdar ◽  
Kuntal Ghosh ◽  
Kamales Bhaumik
Keyword(s):  
High Frequency ◽  
The Other ◽  
Linear Filtering ◽  
Multi Scale ◽  
Difference Of Gaussians ◽  
Frequency Components ◽  
Lightness Induction ◽  
Simulation Results ◽  
Model Support ◽  
Mach Band

The perceived lightness of a stimulus depends on its background, a phenomenon known as lightness induction. For instance, the same gray stimulus can look light in one background and dark in another. Moreover, such induction can take place in two directions; in one case, it occurs in the direction of the background lightness known as lightness assimilation, while in the other it occurs opposite to that, known as lightness contrast. The White’s illusion is a typical one which does not completely conform to any of these two processes. In this paper, we have quantified the perceptual strength of the White’s illusion as a function of the width of the background square grating. Based on our results which also corroborate some earlier studies, we propose a linear filtering model inspired from an earlier work dealing with varying Mach band widths. Our model assumes that the for the White’s illusion, where the edges are strong and many in number, and as such the spectrum is rich in high frequency components, the inhibitory surround in the classical Difference-of-Gaussians (DoG) filter gets suppressed, so that the filter essentially reduces to a multi-scale Gaussian one. The simulation results with this model support the present as well as earlier experimental results.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

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