Design of Wide Bandwidth, High-CMRR Voltage and Transadmittance-Mode Instrumentation Amplifier Using a Single CBTA

2019 ◽  
Vol 29 (04) ◽  
pp. 2050060
Author(s):  
Mehmet Sagbas ◽  
Umut Engin Ayten
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
High Gain ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Wide Bandwidth ◽  
Current Output ◽  
Transconductance Amplifier ◽  
Low Offset ◽  
Electronically Tunable

In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18[Formula: see text][Formula: see text]m CMOS process with [Formula: see text][Formula: see text]V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950192
Author(s):  
Zhe Li ◽  
Rui Ma ◽  
Maliang Liu ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Model Stability ◽  
Analysis And Design ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Compensation Technique ◽  
Layout Area ◽  
The Stability

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [Formula: see text]-[Formula: see text] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[Formula: see text]nm 1.2[Formula: see text]V CMOS process, achieving 808[Formula: see text]MHz gain-bandwidth, 119[Formula: see text]dB DC gain, 585[Formula: see text]V/[Formula: see text]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[Formula: see text]V with power consumption of 2.17[Formula: see text]mW and the layout area is 0.011[Formula: see text]mm2.

A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback

2013 ◽  
Vol 748 ◽  
pp. 847-852
Author(s):  
Jun Yang ◽  
Hong Hui Deng ◽  
Rui Zhang ◽  
Yong Sheng Yin
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sample And Hold ◽  
Feedback Capacitor

A high performance sample-and-hold (S/H) circuit with input common mode feedback (ICMFB) is presented. The ICMFB is used to ensure that the input common mode voltage for the sample-and-hold amplifier (SHA) is maintained at a known value during the hold phase of operation in order to reduce the differential output error when the sample capacitor and feedback capacitor has mismatch. Meanwhile, bootstrapped switches are used to lower the switch on-resistance and reduce the effect of switch non-idealities. Then a low power two stage high gain wideband SHA is designed to guarantee the holding accuracy. Hspice simulated results based on SMIC 0.13μm 1P5M CMOS process under 1.2V supply voltage shows a 108.4 dB spurious free dynamic range (SFDR) at Nyquist input @Fs=100MS/s. The designed S/H circuit has been used in the front end of 14-bit 100MS/s Pipelined ADC adapted for single-ended applications.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

Some Precision Electronics for a Scanning Transmission Electron Miscroscope

1974 ◽  
Vol 32 ◽  
pp. 424-425
Author(s):  
J. A. Zubin ◽  
D. C. Woodruff ◽  
J. W. Wiggins
Keyword(s):  
Power Supply ◽  
Integrated Circuit ◽  
High Gain ◽  
Power Supplies ◽  
Instrumentation Amplifier ◽  
Wide Bandwidth ◽  
Transmission Electron ◽  
Scanning Transmission ◽  
Current Sampling ◽  
Commercial Oil

A one ppm stability 100 KV power supply has been built using a commercial oil-insulated power supply inside a wide bandwidth feedback loop assembled from readily available commercial components. Several one ppm stability current sources for magnetic lenses and eight deflection coil drivers have also been assembled from commercial components. The following approach was used for all of the power supplies. A precision variable reference was made by buffering a 10.83 V, type R mercury battery. A wide bandwidth, high gain preamplifier was made using the full capabilities of the Fairchild 725 integrated circuit instrumentation amplifier. Precision main feedback and current sampling resistors were used.

A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

2022 ◽  
Vol 43 (1) ◽  
pp. 012401
Author(s):  
Quan Pan ◽  
Xiongshi Luo
Keyword(s):  
Optical Measurement ◽  
Supply Voltage ◽  
Electrical Measurement ◽  
High Gain ◽  
Input Device ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Inductive Peaking ◽  
Capacitive Loading

Abstract This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

scholarly journals High CMRR Voltage Mode Instrumentation Amplifier Using a New CMOS Differential Difference Current Conveyor Realization

2020 ◽  
Vol 14 ◽  
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Current Source ◽  
Low Noise ◽  
Current Conveyor ◽  
Instrumentation Amplifier ◽  
Wide Bandwidth ◽  
Voltage Mode ◽  
Constant Bias ◽  
Adaptive Biasing

This paper describes a new CMOS realization of differential difference current conveyor circuit. The proposed design offers enhanced characteristics compared to DDCC circuits previously exhibited in the literature. It is characterized by a wide dynamic range with good accuracy thanks to use of adaptive biasing circuit instead of a constant bias current source as well as a wide bandwidth (560 MHz) and a low parasitic resistance at terminal X about 6.86 Ω. A voltage mode instrumentation amplifier circuit (VMIA) composed of a DDCC circuit and two active grounded resistances is shown as application. The proposed VMIA circuit is intended for high frequency applications. This configuration offers significant improvement in accuracy as compared to the state of the art. It is characterized by a controllable gain, a large dynamic range with THD less than 0.27 %, a low noise density (22 nV/Hz1/2) with a power consumption about 0.492 mW and a wide bandwidth nearly 83 MHz. All proposed circuits are simulated by TSPICE using CMOS 0.18 μm TSMC technology with ± 0.8 V supply voltage to verify the theoretical results.

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