A High Gain, 808MHz GBW Four-Stage OTA in 65nm CMOS

2019 ◽  
Vol 28 (11) ◽  
pp. 1950192
Author(s):  
Zhe Li ◽  
Rui Ma ◽  
Maliang Liu ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Model Stability ◽  
Analysis And Design ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Compensation Technique ◽  
Layout Area ◽  
The Stability

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath [Formula: see text]-[Formula: see text] compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65[Formula: see text]nm 1.2[Formula: see text]V CMOS process, achieving 808[Formula: see text]MHz gain-bandwidth, 119[Formula: see text]dB DC gain, 585[Formula: see text]V/[Formula: see text]s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2[Formula: see text]V with power consumption of 2.17[Formula: see text]mW and the layout area is 0.011[Formula: see text]mm2.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

Design of Wide Bandwidth, High-CMRR Voltage and Transadmittance-Mode Instrumentation Amplifier Using a Single CBTA

2019 ◽  
Vol 29 (04) ◽  
pp. 2050060
Author(s):  
Mehmet Sagbas ◽  
Umut Engin Ayten
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
High Gain ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Wide Bandwidth ◽  
Current Output ◽  
Transconductance Amplifier ◽  
Low Offset ◽  
Electronically Tunable

In this work, a high-performance voltage and current output instrumentation amplifier circuit is proposed. The proposed circuit also has voltage-mode (VM) and transadmittance-mode (TAM) outputs at a time. It employs a single current backward transconductance amplifier (CBTA) and a grounded resistor. It has the advantage of having low input and high output impedances which makes it easy for cascadability. The presented circuit has electronically tunable property due to the bias current of the CBTA. The validity of the proposed circuit is demonstrated by PSPICE simulations using a 0.18[Formula: see text][Formula: see text]m CMOS process with [Formula: see text][Formula: see text]V supply voltage. Simulation results show that the proposed circuit has a high common mode rejection ratio (CMRR), wide bandwidth, low offset and high gain properties.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

scholarly journals 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

2021 ◽  
Vol 11 (4) ◽  
pp. 37
Author(s):  
Andrea Ballo ◽  
Salvatore Pennisi ◽  
Giuseppe Scotti
Keyword(s):  
Supply Voltage ◽  
Current Control ◽  
Cmos Inverter ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Quiescent Current ◽  
Bulk Technology ◽  
Inverter Topology

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

2022 ◽  
Vol 43 (1) ◽  
pp. 012401
Author(s):  
Quan Pan ◽  
Xiongshi Luo
Keyword(s):  
Optical Measurement ◽  
Supply Voltage ◽  
Electrical Measurement ◽  
High Gain ◽  
Input Device ◽  
Cmos Process ◽  
Transimpedance Amplifier ◽  
Bandwidth Enhancement ◽  
Inductive Peaking ◽  
Capacitive Loading

Abstract This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation

2013 ◽  
Vol 380-384 ◽  
pp. 3275-3278
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Hai Huang ◽  
Chang Chun Dong
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
High Gain ◽  
Op Amp ◽  
Rail To Rail ◽  
Dc Gain ◽  
Low Power Dissipation ◽  
Static Power ◽  
Low Supply Voltage

An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.

Analog Integrated Circuit Optimization

2020 ◽  
pp. 95-130
Author(s):  
Houda Daoud ◽  
Dalila Laouej ◽  
Jihene Mallek ◽  
Mourad Loulou
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Pso Algorithm ◽  
Circuit Optimization ◽  
Ultra Low Power ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Threshold Voltages ◽  
Dc Gain ◽  
Low Threshold

This chapter presents a novel telescopic operational transconductance amplifier (OTA) using the bulk-driven MOS technique. This circuit is optimized for ultra-low power applications such as biomedical devices. The proposed the bulk-driven fully differential telescopic OTA with very low threshold voltages is designed under ±0.9V supply voltage. Thanks to the particle swarm optimization (PSO) algorithm, the circuit achieves high performances. The OTA simulation results present a DC gain of 63.6dB, a GBW of 2.8MHz, a phase margin (PM) of 55.8degrees and an input referred noise of 265.3nV/√Hz for a low bias current of 52nA.

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